MPC8544DS Freescale Semiconductor, MPC8544DS Datasheet - Page 22

• Manufacturer Part Number: MPC8544DS
• Description: BOARD DEVELOPMENT SYSTEM 8544
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8544DS

• Contents: Board
• Processor To Be Evaluated: MPC8544E
• Data Bus Width: 32 bit
• Interface Type: Ethernet, I2C
• Operating Supply Voltage: - 0.3 V to + 1.1 V
• Leaded Process Compatible: Yes
• Peak Reflow Compatible (260 C): Yes
• Rohs Compliant: Yes
• For Use With/related Products: MPC8544
• For Use With: PPC8544EVTANG - EVAL MPC8544 783FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Paragraph
Number
12.5.1.3
12.5.1.4
12.5.1.5
12.5.1.6
12.5.2
12.5.2.1
12.5.2.2
12.5.2.3
12.6
12.6.1
12.6.1.1
12.6.1.2
12.6.2
12.6.2.1
12.6.2.2
12.6.2.3
12.6.2.4
12.6.3
12.6.4
12.6.5
12.6.5.1
12.6.5.2
12.6.5.3
12.6.5.4
12.6.5.5
12.6.5.6
12.6.5.7
12.7
13.1
13.1.1
13.1.2
13.2
13.2.1
13.2.2
13.3
13.3.1
13.3.1.1
xxii
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Security Controller..................................................................................................... 12-104
Power-Saving Mode................................................................................................... 12-115
Overview........................................................................................................................ 13-1
External Signal Descriptions ......................................................................................... 13-3
Memory Map/Register Definition ................................................................................. 13-4
Channel Interrupts.................................................................................................. 12-103
Assignment of EUs to Channels ............................................................................ 12-104
Bus Transfers ......................................................................................................... 12-105
Snooping by Caches............................................................................................... 12-108
Controller Interrupts .............................................................................................. 12-108
Controller Registers ............................................................................................... 12-109
Features...................................................................................................................... 13-1
Modes of Operation ................................................................................................... 13-2
Signal Overview ........................................................................................................ 13-3
Detailed Signal Descriptions ..................................................................................... 13-3
Register Descriptions................................................................................................. 13-6
Crypto-Channel Current Descriptor Pointer Registers 1–4 (CCDPRn) ............ 12-100
Fetch FIFO Address Registers 1–4 (FFn).......................................................... 12-101
Crypto-Channel 1–4 Descriptor Buffers [0–7] (DBn[0–7]) .............................. 12-102
Link Table Buffer Registers (Scatter or Gather)—LTB0–3 .............................. 12-102
Channel Done Interrupt ..................................................................................... 12-103
Channel Error Interrupt...................................................................................... 12-103
Channel Reset .................................................................................................... 12-103
Channel Priority Arbitration .............................................................................. 12-105
Channel Round-Robin Arbitration .................................................................... 12-105
Arbitration for Use of the Controller and Buses................................................ 12-106
System Bus Master Reads ................................................................................. 12-107
System Bus Master Writes................................................................................. 12-107
System Bus Slave Transactions (Reads and Writes) ......................................... 12-107
EU Assignment Status Register (EUASR) ........................................................ 12-109
Interrupt Mask Register (IMR).......................................................................... 12-110
Interrupt Status Register (ISR) ...........................................................................12-111
Interrupt Clear Register (ICR) ........................................................................... 12-112
ID Register......................................................................................................... 12-113
IP Block Revision Register................................................................................ 12-113
Master Control Register (MCR) ........................................................................ 12-114
Receiver Buffer Registers (URBR0, URBR1) (ULCR[DLAB] = 0) .................... 13-6
Contents
Chapter 13
DUART
Title
Freescale Semiconductor
Number
Page