MPC8544DS Freescale Semiconductor, MPC8544DS Datasheet - Page 256
![BOARD DEVELOPMENT SYSTEM 8544](/photos/37/58/375876/mpc8544e_sml.jpg)
MPC8544DS
Manufacturer Part Number
MPC8544DS
Description
BOARD DEVELOPMENT SYSTEM 8544
Manufacturer
Freescale Semiconductor
Series
PowerQUICC III™r
Type
MPUr
Datasheets
1.MPC8544VTALF.pdf
(117 pages)
2.MPC8544VTALF.pdf
(2 pages)
3.MPC8544VTALF.pdf
(1340 pages)
4.MPC8544DS.pdf
(2 pages)
Specifications of MPC8544DS
Contents
Board
Processor To Be Evaluated
MPC8544E
Data Bus Width
32 bit
Interface Type
Ethernet, I2C
Operating Supply Voltage
- 0.3 V to + 1.1 V
Leaded Process Compatible
Yes
Peak Reflow Compatible (260 C)
Yes
Rohs Compliant
Yes
For Use With/related Products
MPC8544
For Use With
PPC8544EVTANG - EVAL MPC8544 783FCPBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- MPC8544VTALF PDF datasheet
- MPC8544VTALF PDF datasheet #2
- MPC8544VTALF PDF datasheet #3
- MPC8544DS PDF datasheet #4
- Current page: 256 of 1340
- Download datasheet (12Mb)
Core Register Summary
6.12.5.5
6.12.5.6
6-38
Reset
32–34
36–45
46–47
48–51
52–55
SPR 630
Reset
Bits
35
56
57
58
59
60
61
62
63
SPR 628
W
R
W
R
32
32
TLBSELD TLBSEL default value. The default value to be loaded in MAS0[TLBSEL] on a TLB miss exception.
TIDSELD TID default selection value. A 2-bit field that specifies which of the current PID registers should be used
TSIZED
—
Name
X0D
X1D
WD
MD
GD
ED
34
Table 6-32. MAS4 Field Descriptions—Hardware Replacement Assist Configuration
—
—
—
—
ID
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
TLBSELD
MAS Register 4 (MAS4)
MAS Register 6 (MAS6)
—
35
Reserved, should be cleared.
0 TLB0
1 TLB1
Reserved, should be cleared.
to load the MAS1[TID] field on a TLB miss exception.
The e500 implementation defines this field as follows:
00 PID0
01 PID1
10 PID2
11 TIDZ (0x00) (all zeros)
Reserved, should be cleared.
Default TSIZE value. Specifies the default value to be loaded into MAS1[TSIZE] on a TLB miss exception.
Reserved, should be cleared.
Default X0 value. Specifies the default value to be loaded into MAS2[X0] on a TLB miss exception.
Default X1 value. Specifies the default value to be loaded into MAS2[X1] on a TLB miss exception.
Default W value. Specifies the default value to be loaded into MAS2[W] on a TLB miss exception.
Default I value. Specifies the default value to be loaded into MAS2[I] on a TLB miss exception.
Default M value. Specifies the default value to be loaded into MAS2[M] on a TLB miss exception.
Default G value. Specifies the default value to be loaded into MAS2[G] on a TLB miss exception.
Default E value. Specifies the default value to be loaded into MAS2[E] on a TLB miss exception.
36
39 40
—
Figure 6-47. MAS Register 4 (MAS4)
Figure 6-48. MAS Register 6 (MAS6)
SPID0
45
TIDSELD
46
47
All zeros
All zeros
47 48
48
Description
—
50 51 52
TSIZED — X0D X1D WD ID MD GD ED
55 56
—
57
Access: Supervisor read/write
Access: Supervisor read/write
58
Freescale Semiconductor
59
60 61
62
62
SAS
63
63
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