MPC8544DS Freescale Semiconductor, MPC8544DS Datasheet - Page 397

• Manufacturer Part Number: MPC8544DS
• Description: BOARD DEVELOPMENT SYSTEM 8544
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8544DS

• Contents: Board
• Processor To Be Evaluated: MPC8544E
• Data Bus Width: 32 bit
• Interface Type: Ethernet, I2C
• Operating Supply Voltage: - 0.3 V to + 1.1 V
• Leaded Process Compatible: Yes
• Peak Reflow Compatible (260 C): Yes
• Rohs Compliant: Yes
• For Use With/related Products: MPC8544
• For Use With: PPC8544EVTANG - EVAL MPC8544 783FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

If DDR_SDRAM_CFG_2[SR_IE] is set, the IRQ_OUT signal from the interrupt controller is then
automatically detected by the DDR controller, which immediately causes main memory to enter
self-refresh mode. See
(DDR_SDRAM_CFG_2),”
These fields in the appropriate registers in the PIC must be set for self refresh to function:
See
Section 10.3.7.2, “External Interrupt Destination Registers (EIDR0–EIDR11),”
registers.
Note that this application precludes any other simultaneous use of IRQ_OUT.
9.6.3.2
The DDR controller also has a software-programmable bit, DDR_SDRAM_CFG_2[FRC_SR], that
immediately puts main memory into self-refresh mode. See
Configuration 2 (DDR_SDRAM_CFG_2),”
It is expected that a critical interrupt routine triggered by an external voltage sensing device will have time
to set this bit.
9.6.3.3
The DDR controller offers an initialization bypass feature (DDR_SDRAM_CFG[BI]), which system
designers may use to prevent re-initialization of main memory during system power-on following an
abnormal shutdown. See
for information on this bit and
a discussion of avoiding possible ECC errors in this mode.
Note that the DDR controller will automatically wait 200 DRAM cycles before issuing any command after
the assertion of MCKE[0:3] when this mode is used.
Freescale Semiconductor
•
•
Section 10.3.7.1, “External Interrupt Vector/Priority Registers (EIVPR0–EIVPR11),”
EIVPRn[PRIORITY] should be set to 0xF (highest priority)
EIDRn[EP] should be set in order to route the incoming signal to IRQ_OUT
Software Based Self-Refresh
Bypassing Re-initialization During Battery-Backed Operation
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Section 9.4.1.8, “DDR SDRAM Control Configuration 2
Section 9.4.1.7, “DDR SDRAM Control Configuration (DDR_SDRAM_CFG),”
for further information on this bit.
Section 9.4.1.15, “DDR Initialization Address (DDR_INIT_ADDR),”
for a description of this register.
Section 9.4.1.8, “DDR SDRAM Control
for descriptions of these
DDR Memory Controller
and
9-73
for