MPC8544DS Freescale Semiconductor, MPC8544DS Datasheet - Page 164

• Manufacturer Part Number: MPC8544DS
• Description: BOARD DEVELOPMENT SYSTEM 8544
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8544DS

• Contents: Board
• Processor To Be Evaluated: MPC8544E
• Data Bus Width: 32 bit
• Interface Type: Ethernet, I2C
• Operating Supply Voltage: - 0.3 V to + 1.1 V
• Leaded Process Compatible: Yes
• Peak Reflow Compatible (260 C): Yes
• Rohs Compliant: Yes
• For Use With/related Products: MPC8544
• For Use With: PPC8544EVTANG - EVAL MPC8544 783FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Reset, Clocking, and Initialization
4.3.1.2
An alternate configuration space can be accessed by configuring the ALTCBAR and ALTCAR registers.
These are intended to be used with the boot sequencer to allow the boot sequencer to access an alternate
1-Mbyte region of configuration space. By loading the proper boot sequencer command in the serial ROM,
the base address in the ALTCBAR can be combined with the 20 bits of address offset supplied from the
serial ROM to generate a 36-bit address that is mapped to the target specified in ALTCAR. Thus, by
configuring these registers, the boot sequencer has access to the entire memory map, one 1-Mbyte block
at a time. See
4.3.1.2.1
Figure 4-2
Table 4-6
4.3.1.2.2
Figure 4-3
4-6
24–31
8–23
Bits
0–7
Offset 0x0_0010
Reset
Offset 0x0_0008
Reset
W
W
R
R
EN
BASE_ADDR Identifies the16 most significant address bits of an alternate window used for configuration accesses.
0
0
defines the bit fields of ALTCBAR.
shows the fields of ALTCBAR.
shows the fields of ALTCAR.
Name
1
Accessing Alternate Configuration Space
—
—
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Section 11.4.5, “Boot Sequencer Mode,”
The enable bit in the ALTCAR register should be cleared either by the boot
sequencer or by the boot code that executes after the boot sequencer has
completed its configuration operations. This prevents problems with
incorrect mappings if subsequent configuration of the local access windows
uses a different target mapping for the address specified in ALTCBAR.
Alternate Configuration Base Address Register (ALTCBAR)
Alternate Configuration Attribute Register (ALTCAR)
Figure 4-2. Alternate Configuration Base Address Register (ALTCBAR)
—
Figure 4-3. Alternate Configuration Attribute Register (ALTCAR)
Write reserved, read = 0
Write reserved, read = 0
—
7
7
8
8
Table 4-6. ALTCBAR Bit Settings
TRGT_ID
11 12
NOTE
BASE_ADDR
All zeros
All zeros
for more information.
Description
—
23 24
Freescale Semiconductor
Access: Read/Write
Access: Read/Write
—
31
31