MPC8544DS Freescale Semiconductor, MPC8544DS Datasheet - Page 45
![BOARD DEVELOPMENT SYSTEM 8544](/photos/37/58/375876/mpc8544e_sml.jpg)
MPC8544DS
Manufacturer Part Number
MPC8544DS
Description
BOARD DEVELOPMENT SYSTEM 8544
Manufacturer
Freescale Semiconductor
Series
PowerQUICC III™r
Type
MPUr
Datasheets
1.MPC8544VTALF.pdf
(117 pages)
2.MPC8544VTALF.pdf
(2 pages)
3.MPC8544VTALF.pdf
(1340 pages)
4.MPC8544DS.pdf
(2 pages)
Specifications of MPC8544DS
Contents
Board
Processor To Be Evaluated
MPC8544E
Data Bus Width
32 bit
Interface Type
Ethernet, I2C
Operating Supply Voltage
- 0.3 V to + 1.1 V
Leaded Process Compatible
Yes
Peak Reflow Compatible (260 C)
Yes
Rohs Compliant
Yes
For Use With/related Products
MPC8544
For Use With
PPC8544EVTANG - EVAL MPC8544 783FCPBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- MPC8544VTALF PDF datasheet
- MPC8544VTALF PDF datasheet #2
- MPC8544VTALF PDF datasheet #3
- MPC8544DS PDF datasheet #4
- Current page: 45 of 1340
- Download datasheet (12Mb)
Figure
Number
1-1
1-2
1-3
1-4
1-5
1-6
1-7
1-8
2-1
2-2
2-3
2-4
2-5
2-6
2-7
2-8
3-1
3-2
3-3
4-1
4-2
4-3
4-4
4-5
4-6
4-7
5-1
5-2
5-3
5-4
5-5
5-6
5-7
5-8
Freescale Semiconductor
MPC8544E Block Diagram .................................................................................................... 1-2
Integrated Security Engine Functional Blocks...................................................................... 1-16
Processing Transactions Across the On-Chip Fabric............................................................ 1-21
Multifunction Router Application Enabled by Local Bus, PCI Express,
Multifunction Printer Application Enabled by Local Bus, PCI Express,
Security Appliance Enabled by SEC, Local Bus, PCI, and Ethernet.................................... 1-24
IP SAN Host Adapter Enabled by Local Bus, PCI Express, and Ethernet ........................... 1-25
VoIP Aggregation Application Enabled by Local Bus and Ethernet .................................... 1-26
Local Memory Map Example ................................................................................................. 2-2
Local Access IP Block Revision Register 1 (LAIPBRR1) ..................................................... 2-6
Local Access IP Block Revision Register 2 (LAIPBRR2) ..................................................... 2-6
Local Access Window n Base Address Registers (LAWBAR0–LAWBAR7) ....................... 2-7
Local Access Window n Attributes Registers (LAWAR0–LAWAR7) ................................... 2-7
General Utilities Registers Mapping to Configuration, Control,
PIC Mapping to Configuration, Control, and Status Memory Block ................................... 2-13
Device-Specific Register Mapping to Configuration, Control,
MPC8544E Signal Groupings (1/3)........................................................................................ 3-2
MPC8544E Signal Groupings (2/3) (Continued).................................................................... 3-3
MPC8544E Signal Groupings (3/3) (Continued).................................................................... 3-4
Configuration, Control, and Status Register Base Address Register (CCSRBAR)................ 4-5
Alternate Configuration Base Address Register (ALTCBAR) ............................................... 4-6
Alternate Configuration Attribute Register (ALTCAR) ......................................................... 4-6
Boot Page Translation Register (BPTR) ................................................................................. 4-7
Power-On Reset Sequence .................................................................................................... 4-10
Clock Subsystem Block Diagram ......................................................................................... 4-24
RTC and Core Timer Facilities Clocking Options ................................................................ 4-26
e500 Core Complex Block Diagram ....................................................................................... 5-2
Vector and Floating-Point APUs............................................................................................. 5-5
Four-Stage MU Pipeline, Showing Divide Bypass................................................................. 5-7
Three-Stage Load/Store Unit .................................................................................................. 5-8
Instruction Pipeline Flow ...................................................................................................... 5-14
GPR Issue Queue (GIQ) ....................................................................................................... 5-15
e500 Core Programming Model............................................................................................ 5-17
MMU Structure ..................................................................................................................... 5-23
PCI, and Ethernet ............................................................................................................. 1-22
PCI, and Ethernet ............................................................................................................. 1-23
and Status Memory Block ................................................................................................ 2-12
and Status Memory Block ................................................................................................ 2-14
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
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