MPC8544DS Freescale Semiconductor, MPC8544DS Datasheet - Page 65
MPC8544DS
Manufacturer Part Number
MPC8544DS
Description
BOARD DEVELOPMENT SYSTEM 8544
Manufacturer
Freescale Semiconductor
Series
PowerQUICC III™r
Type
MPUr
Datasheets
1.MPC8544VTALF.pdf
(117 pages)
2.MPC8544VTALF.pdf
(2 pages)
3.MPC8544VTALF.pdf
(1340 pages)
4.MPC8544DS.pdf
(2 pages)
Specifications of MPC8544DS
Contents
Board
Processor To Be Evaluated
MPC8544E
Data Bus Width
32 bit
Interface Type
Ethernet, I2C
Operating Supply Voltage
- 0.3 V to + 1.1 V
Leaded Process Compatible
Yes
Peak Reflow Compatible (260 C)
Yes
Rohs Compliant
Yes
For Use With/related Products
MPC8544
For Use With
PPC8544EVTANG - EVAL MPC8544 783FCPBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- MPC8544VTALF PDF datasheet
- MPC8544VTALF PDF datasheet #2
- MPC8544VTALF PDF datasheet #3
- MPC8544DS PDF datasheet #4
- Current page: 65 of 1340
- Download datasheet (12Mb)
Figure
Number
18-126
18-127
18-128
18-129
18-130
18-131
19-1
19-2
19-3
19-4
19-5
19-6
19-7
19-8
19-9
19-10
19-11
19-12
19-13
19-14
19-15
19-16
19-17
19-18
19-19
19-20
19-21
19-22
19-23
19-24
19-25
19-26
19-27
19-28
20-1
20-2
20-3
20-4
20-5
20-6
20-7
Freescale Semiconductor
Address Invariant Byte Ordering—4 bytes Outbound........................................................ 18-99
Address Invariant Byte Ordering—4 bytes Inbound ........................................................ 18-100
Address Invariant Byte Ordering—8 bytes Outbound...................................................... 18-100
Address Invariant Byte Ordering—2 bytes Inbound ........................................................ 18-100
PEX_CONFIG_DATA Byte Ordering.............................................................................. 18-101
WAKE Generation Example ............................................................................................ 18-109
POR PLL Status Register (PORPLLSR) .............................................................................. 19-5
POR Boot Mode Status Register (PORBMSR) .................................................................... 19-6
POR I/O Impedance Status and Control Register (PORIMPSCR) ....................................... 19-7
POR Device Status Register (PORDEVSR) ......................................................................... 19-8
POR Debug Mode Status Register (PORDBGMSR).......................................................... 19-10
POR Device Status Register 2 (PORDEVSR2) .................................................................. 19-10
POR Configuration Register (GPPORCR) ......................................................................... 19-11
General-Purpose I/O Control Register (GPIOCR).............................................................. 19-12
General-Purpose Output Data Register (GPOUTDR) ........................................................ 19-12
General-Purpose Input Data Register (GPINDR) ............................................................... 19-13
Alternate Function Pin Multiplex Control Register (PMUXCR) ....................................... 19-13
Device Disable Register (DEVDISR)................................................................................. 19-14
Power Management Control and Status Register (POWMGTCSR) ................................... 19-16
Machine Check Summary Register (MCPSUMR) ............................................................. 19-17
Reset Request Status and Control Register (RSTRSCR).................................................... 19-18
Processor Version Register (PVR) ...................................................................................... 19-19
System Version Register (SVR).......................................................................................... 19-19
Reset Control Register (RSTCR)........................................................................................ 19-20
LBC Voltage Select Control Register (LBIUVSELCR) ..................................................... 19-20
DDR Calibration Status Register (DDRCSR)..................................................................... 19-21
DDR Control Driver Register (DDRCDR) ......................................................................... 19-21
DDR Clock Disable Register (DDRCLKDR) .................................................................... 19-22
Clock Out Control Register (CLKOCR)............................................................................. 19-23
SerDes 1 Control Register 1 (SRDS1CR1)......................................................................... 19-24
SerDes 2 Control Register 1 (SRDS2CR1)......................................................................... 19-25
SerDes 2 Control Register 3 (SRDS2CR3)......................................................................... 19-26
e500 Core Power Management State Diagram ................................................................... 19-27
MPC8544E Power Management Handshaking Signals...................................................... 19-32
Performance Monitor Block Diagram................................................................................... 20-2
Performance Monitor Global Control Register (PMGC0).................................................... 20-5
Performance Monitor Local Control Register A0 (PMLCA0) ............................................. 20-6
Performance Monitor Local Control A Registers (PMLCA1–PMLCA9)............................ 20-7
Performance Monitor Local Control Register B0 (PMLCB0).............................................. 20-8
Performance Monitor Local Control Register B (PMLCB1–PMLCB9) .............................. 20-9
Performance Monitor Counter Register 0 (PMC0)............................................................. 20-10
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Figures
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Number
Page
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