MPC8544DS Freescale Semiconductor, MPC8544DS Datasheet - Page 69
![BOARD DEVELOPMENT SYSTEM 8544](/photos/37/58/375876/mpc8544e_sml.jpg)
MPC8544DS
Manufacturer Part Number
MPC8544DS
Description
BOARD DEVELOPMENT SYSTEM 8544
Manufacturer
Freescale Semiconductor
Series
PowerQUICC III™r
Type
MPUr
Datasheets
1.MPC8544VTALF.pdf
(117 pages)
2.MPC8544VTALF.pdf
(2 pages)
3.MPC8544VTALF.pdf
(1340 pages)
4.MPC8544DS.pdf
(2 pages)
Specifications of MPC8544DS
Contents
Board
Processor To Be Evaluated
MPC8544E
Data Bus Width
32 bit
Interface Type
Ethernet, I2C
Operating Supply Voltage
- 0.3 V to + 1.1 V
Leaded Process Compatible
Yes
Peak Reflow Compatible (260 C)
Yes
Rohs Compliant
Yes
For Use With/related Products
MPC8544
For Use With
PPC8544EVTANG - EVAL MPC8544 783FCPBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- MPC8544VTALF PDF datasheet
- MPC8544VTALF PDF datasheet #2
- MPC8544VTALF PDF datasheet #3
- MPC8544DS PDF datasheet #4
- Current page: 69 of 1340
- Download datasheet (12Mb)
Table
Number
6-24
6-25
6-26
6-27
6-28
6-29
6-30
6-31
6-32
6-33
6-34
6-35
6-36
6-37
6-38
6-39
6-40
6-41
6-42
6-43
6-44
6-45
6-46
1
7-2
7-3
7-4
7-5
7-6
7-7
7-8
7-9
7-10
7-11
7-12
7-13
7-14
7-15
7-16
7-17
7-18
Freescale Semiconductor
MMUCSR0 Field Descriptions............................................................................................. 6-32
MMUCFG Field Descriptions .............................................................................................. 6-33
TLB0CFG Field Descriptions ............................................................................................... 6-33
TLB1CFG Field Descriptions ............................................................................................... 6-34
MAS0 Field Descriptions—MMU Read/Write and Replacement Control .......................... 6-35
MAS1 Field Descriptions—Descriptor Context and Configuration Control........................ 6-36
MAS2 Field Descriptions—EPN and Page Attributes ......................................................... 6-36
MAS3 Field Descriptions–RPN and Access Control ........................................................... 6-37
MAS4 Field Descriptions—Hardware Replacement Assist Configuration.......................... 6-38
MAS6—TLB Search Context Register 0.............................................................................. 6-39
MAS 7 Field Descriptions—High Order RPN ..................................................................... 6-39
DBCR0 Field Descriptions ................................................................................................... 6-40
DBCR1 Field Descriptions ................................................................................................... 6-41
DBCR2 Field Descriptions ................................................................................................... 6-42
DBSR Field Descriptions...................................................................................................... 6-44
SPEFSCR Field Descriptions................................................................................................ 6-45
ACC FIeld Descriptions........................................................................................................ 6-47
Supervisor-Level PMRs (PMR[5] = 1) ................................................................................. 6-48
User-Level PMRs (PMR[5] = 0) (Read Only)...................................................................... 6-48
PMGC0 Field Descriptions ................................................................................................... 6-49
PMLCa0–PMLCa3 Field Descriptions ................................................................................. 6-50
PMLCb0–PMLCb3 Field Descriptions ................................................................................ 6-51
PMC0–PMC3 Field Descriptions ......................................................................................... 6-52
Available L2 Cache/SRAM Configurations............................................................................ 7-3
Way Selection for SRAM Accesses........................................................................................ 7-6
L2/SRAM Memory-Mapped Registers................................................................................... 7-9
L2CTL Field Descriptions .................................................................................................... 7-10
L2CEWARn Field Descriptions............................................................................................ 7-14
L2CEWAREAn Field Descriptions ...................................................................................... 7-14
L2CEWCRn Field Descriptions............................................................................................ 7-15
L2SRBARn Field Descriptions............................................................................................. 7-16
L2SRBAREAn Field Descriptions ....................................................................................... 7-17
L2ERRINJHI Field Description............................................................................................ 7-18
L2ERRINJLO Field Description .......................................................................................... 7-19
L2ERRINJCTL Field Descriptions....................................................................................... 7-19
L2CAPTDATAHI Field Description..................................................................................... 7-20
L2CAPTDATALO Field Description.................................................................................... 7-20
L2CAPTECC Field Descriptions .......................................................................................... 7-21
L2ERRDET Field Descriptions ............................................................................................ 7-21
L2ERRDIS Field Descriptions.............................................................................................. 7-22
L2ERRINTEN Field Descriptions ........................................................................................ 7-23
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Tables
Title
Number
Page
lxix
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