MPC8544DS Freescale Semiconductor, MPC8544DS Datasheet - Page 760
![BOARD DEVELOPMENT SYSTEM 8544](/photos/37/58/375876/mpc8544e_sml.jpg)
MPC8544DS
Manufacturer Part Number
MPC8544DS
Description
BOARD DEVELOPMENT SYSTEM 8544
Manufacturer
Freescale Semiconductor
Series
PowerQUICC III™r
Type
MPUr
Datasheets
1.MPC8544VTALF.pdf
(117 pages)
2.MPC8544VTALF.pdf
(2 pages)
3.MPC8544VTALF.pdf
(1340 pages)
4.MPC8544DS.pdf
(2 pages)
Specifications of MPC8544DS
Contents
Board
Processor To Be Evaluated
MPC8544E
Data Bus Width
32 bit
Interface Type
Ethernet, I2C
Operating Supply Voltage
- 0.3 V to + 1.1 V
Leaded Process Compatible
Yes
Peak Reflow Compatible (260 C)
Yes
Rohs Compliant
Yes
For Use With/related Products
MPC8544
For Use With
PPC8544EVTANG - EVAL MPC8544 783FCPBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- MPC8544VTALF PDF datasheet
- MPC8544VTALF PDF datasheet #2
- MPC8544VTALF PDF datasheet #3
- MPC8544DS PDF datasheet #4
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- Download datasheet (12Mb)
Enhanced Three-Speed Ethernet Controllers
15.5.3.1.4
The interrupt mask register provides control over which possible interrupt events in the IEVENT register
are permitted to participate in generating hardware interrupts to the PIC. All implemented bits in this
register are R/W and cleared upon a hardware reset. If the corresponding bits in both the IEVENT and
IMASK registers are set, the PIC will receive an interrupt (for each eTSEC these are grouped into transmit,
receive, and error/diagnostic interrupts). The interrupt signal remains asserted until either the IEVENT bit
is cleared, by writing a 1 to it, or by writing a 0 to the corresponding IMASK bit.
Figure 15-5
15-28
Bits
29
30
31
Name
PERR
DPE
FIQ
describes the IMASK register.
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Interrupt Mask Register (IMASK)
Filed frame to invalid receive queue. This bit indicates that either the receive queue filer chose to DMA a
received frame to a disabled RxBD ring, or that no rule in the filer table could be matched.
0 Received frames filed to valid queues or rejected. Note that a frame may be rejected if the filer has
1 Received frames filed to RxBD rings that are not enabled. The frame is discarded. If bit FIR is also set
which is likely to compromise the validity of recently transferred frames.
0 No parity errors detected.
1 Data held in the FIFO or filer arrays is expected to be corrupted due to a parity error.
unambiguously, due to encapsulated header type fields contradicting each other.
0 Received frame parsed successfully.
1 Received frame parse revealed header inconsistencies.
Internal data parity error. This bit indicates that the eTSEC has detected a parity error on its stored data,
Receive frame parse error for TCP/IP off-load. This bit indicates that a received frame could not be parsed
insufficient time to reach a conclusive result between frames, in which case bit FIR is set.
this indicates that the filer exhausted all of its table entries without a rule match.
Table 15-7. IEVENT Field Descriptions (continued)
Description
Freescale Semiconductor
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