MPC8544DS Freescale Semiconductor, MPC8544DS Datasheet - Page 251

• Manufacturer Part Number: MPC8544DS
• Description: BOARD DEVELOPMENT SYSTEM 8544
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8544DS

• Contents: Board
• Processor To Be Evaluated: MPC8544E
• Data Bus Width: 32 bit
• Interface Type: Ethernet, I2C
• Operating Supply Voltage: - 0.3 V to + 1.1 V
• Leaded Process Compatible: Yes
• Peak Reflow Compatible (260 C): Yes
• Rohs Compliant: Yes
• For Use With/related Products: MPC8544
• For Use With: PPC8544EVTANG - EVAL MPC8544 783FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6.12.4
6.12.4.1
Freescale Semiconductor
32–48
49–52
53–57
58–59
60–61
62–63
Reset 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 1
32–39
40–43
44–47
Bits
Bits
SPR 688
48
49
W
R
32
MAXSIZE Maximum page size of TLB0
MINSIZE Minimum page size of TLB0
PIDSIZE
ASSOC
NTLBS
NPIDS
IPROT
MAVN
Name
Name
AVAIL
—
—
TLB Configuration Registers (TLB n CFG)
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
ASSOC
TLB0 Configuration Register 0 (TLB0CFG)
Reserved, should be cleared.
Number of PID registers, a 4-bit field that indicates the number of PID registers provided by the processor.
The e500 implements three PIDs.
PID register size. The 5-bit value of PIDSIZE is one less than the number of bits in each of the PID
registers implemented by the processor. The processor implements only the least significant PIDSIZE+1
bits in the PID registers.
00111 indicates 8-bit registers. This is the value presented by the e500.
Reserved, should be cleared.
Number of TLBs. The value of NTLBS is one less than the number of software-accessible TLB structures
that are implemented by the processor. NTLBS is set to one less than the number of TLB structures so
that its value matches the maximum value of MAS0[TLBSEL].
00 1 TLB
01 2 TLBs. This is the value presented by the e500.
10 3 TLBs
11 4 TLBs
MMU architecture version number. Indicates the version number of the architecture of the MMU
implemented by the processor. 0b00 indicates version 1.0.
Associativity of TLB0
0x02 indicates associativity is 2-way set associative
0x1 indicates smallest page size is 4K
0x1 indicates maximum page size is 4K
Invalidate protect capability of TLB0
0 Indicates invalidate protection capability not supported
Page size availability of TLB0
0 No variable-sized pages available (MINSIZE = MAXSIZE)
Figure 6-41. TLB Configuration Register 0 (TLB0CFG)
39 40
MINSIZE
Table 6-26. TLB0CFG Field Descriptions
Table 6-25. MMUCFG Field Descriptions
43 44
MAXSIZE
47
IPROT AVAIL
48
0
Description
Description
49
0
50 51 52
0 0 0 0 1 0 0 0 0 0 0 0 0 0
—
Access: Supervisor read only
NENTRY
Core Register Summary
6-33
63