MPC8544DS Freescale Semiconductor, MPC8544DS Datasheet - Page 994
![BOARD DEVELOPMENT SYSTEM 8544](/photos/37/58/375876/mpc8544e_sml.jpg)
MPC8544DS
Manufacturer Part Number
MPC8544DS
Description
BOARD DEVELOPMENT SYSTEM 8544
Manufacturer
Freescale Semiconductor
Series
PowerQUICC III™r
Type
MPUr
Datasheets
1.MPC8544VTALF.pdf
(117 pages)
2.MPC8544VTALF.pdf
(2 pages)
3.MPC8544VTALF.pdf
(1340 pages)
4.MPC8544DS.pdf
(2 pages)
Specifications of MPC8544DS
Contents
Board
Processor To Be Evaluated
MPC8544E
Data Bus Width
32 bit
Interface Type
Ethernet, I2C
Operating Supply Voltage
- 0.3 V to + 1.1 V
Leaded Process Compatible
Yes
Peak Reflow Compatible (260 C)
Yes
Rohs Compliant
Yes
For Use With/related Products
MPC8544
For Use With
PPC8544EVTANG - EVAL MPC8544 783FCPBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- MPC8544VTALF PDF datasheet
- MPC8544VTALF PDF datasheet #2
- MPC8544VTALF PDF datasheet #3
- MPC8544DS PDF datasheet #4
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- Download datasheet (12Mb)
PCI Bus Interface
17-10
PCI_SERR
PCI_STOP
PCI_TRDY
Signal
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Table 17-2. PCI Interface Signals—Detailed Signal Descriptions (continued)
I/O
I/O PCI system error.The PCI system error signal is both an input and output signal on this PCI controller.
I/O Stop.The stop signal is both an input and output signal on this PCI controller.
I/O Target ready. Both an input and output signal on this PCI controller.
O As outputs for the bidirectional PCI system error, these signals operate as described below.
O As outputs for the bidirectional stop, these signals operate as described below.
O As outputs for the bidirectional target ready, these signals operate as described below.
I As inputs for the bidirectional PCI system error, these signals operate as described below.
I As inputs for the bidirectional stop, these signals operate as described below.
I As inputs for the bidirectional target ready, these signals operate as described below.
Meaning
Meaning
Meaning
Meaning
Meaning
Meaning
Timing Assertion/Negation—As specified by PCI Local Bus Specification Rev 2.2
Timing Assertion/Negation—As specified by PCI Local Bus Specification Rev 2.2
Timing Assertion/Negation—As specified by PCI Local Bus Specification Rev 2.2
Timing Assertion/Negation—As specified by PCI Local Bus Specification Rev 2.2
Timing Assertion/Negation—As specified by PCI Local Bus Specification Rev 2.2
Timing Assertion/Negation—As specified by PCI Local Bus Specification Rev 2.2
State
State
State
State
State
State
Asserted—Indicates that an address parity error, a target-abort (when this PCI controller is
Negated—Indicates no error.
Asserted—Indicates that a target (other than this PCI controller) has detected a
Negated—Indicates no error.
Asserted—Indicates that this PCI controller, acting as a PCI target, is requesting that the
Negated—Indicates that the current transaction can continue.
Asserted—Indicates that a target is requesting that the PCI initiator stop the current
Negated—Indicates that the current transaction can continue.
Asserted—Indicates that this PCI controller, acting as a PCI target, can complete the
Negated—Indicates that the PCI initiator needs to wait before this PCI controller, acting as
Asserted—Another PCI target is able to complete the current data phase of a transaction.
Negated—Indicates a wait cycle from another target.
acting as the initiator), or some other system error (where the result is a catastrophic
error) was detected.
catastrophic error.
initiator stop the current transaction.
transaction.
current data phase of a PCI transaction. During a read, this PCI controller asserts
PCI_TRDY to indicate that valid data is present on the data bus. During a write, this
PCI controller asserts PCI_TRDY to indicate that it is prepared to accept data.
a PCI target, can complete the current data phase. During a read, this PCI controller
negates PCI_TRDY to insert a wait cycle when it cannot provide valid data to the
initiator. During a write, this PCI controller negates PCI_TRDY to insert a wait cycle
when it cannot accept data from the initiator.
Description
Freescale Semiconductor
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