MPC8544DS Freescale Semiconductor, MPC8544DS Datasheet - Page 284
![BOARD DEVELOPMENT SYSTEM 8544](/photos/37/58/375876/mpc8544e_sml.jpg)
MPC8544DS
Manufacturer Part Number
MPC8544DS
Description
BOARD DEVELOPMENT SYSTEM 8544
Manufacturer
Freescale Semiconductor
Series
PowerQUICC III™r
Type
MPUr
Datasheets
1.MPC8544VTALF.pdf
(117 pages)
2.MPC8544VTALF.pdf
(2 pages)
3.MPC8544VTALF.pdf
(1340 pages)
4.MPC8544DS.pdf
(2 pages)
Specifications of MPC8544DS
Contents
Board
Processor To Be Evaluated
MPC8544E
Data Bus Width
32 bit
Interface Type
Ethernet, I2C
Operating Supply Voltage
- 0.3 V to + 1.1 V
Leaded Process Compatible
Yes
Peak Reflow Compatible (260 C)
Yes
Rohs Compliant
Yes
For Use With/related Products
MPC8544
For Use With
PPC8544EVTANG - EVAL MPC8544 783FCPBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- MPC8544VTALF PDF datasheet
- MPC8544VTALF PDF datasheet #2
- MPC8544VTALF PDF datasheet #3
- MPC8544DS PDF datasheet #4
- Current page: 284 of 1340
- Download datasheet (12Mb)
L2 Look-Aside Cache/SRAM
Table 7-5
7.3.1.2.2
The L2 cache external write address registers extended address (L2CEWAREAn), shown in
contain the upper 4 bits of the 28-bit L2 cache external write base address.
Table 7-6
7.3.1.2.3
The L2CEWARn/L2CEWAREAn address registers work with the L2 cache external write control
registers 0–3 (L2CEWCRn), shown in
7-14
Offset 0x2_0014
Reset
Offset 0x2_0018
Reset
24–31
28–31
0–23
0–27
Bits
Bits
W
W
R
R
0x2_0024
0x2_0034
0x2_0044
0x2_0028
0x2_0038
0x2_0048
E LOCK
0
0
Figure 7-9. Cache External Write Address Registers Extended Address (L2CEWAREA n )
describes L2CEWARn fields.
describes the fields of L2CEWAREAn.
ADDR
ADDR
Name
Name
1
Figure 7-10. Cache External Write Control Registers (L2CEWCR0–L2CEWCR3)
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
—
—
L2 Cache External Write Address Registers Extended Address 0–3
(L2CEWAREA n )
L2 Cache External Write Control Registers 0–3 (L2CEWCR n )
2
—
3
bits of the base address are in L2CEWAREA n [ADDR].
Reserved
Reserved
address is in L2CEWAR n [ADDR].
Contains the lower 24 bits of the 28-bit L2 cache external write base address. Note that the upper 4
Contains the upper 4 bits of the L2 cache external write base address. Note that the rest of the base
4
Table 7-6. L2CEWAREA n Field Descriptions
Table 7-5. L2CEWAR n Field Descriptions
Figure
7-10, to control cache external write functionality.
—
All zeros
All zeros
Description
Description
SIZMASK
Freescale Semiconductor
Access: Read/Write
Access: Read/Write
27 28
Figure
ADDR
7-9,
31
31
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