MPC8544DS Freescale Semiconductor, MPC8544DS Datasheet - Page 546

• Manufacturer Part Number: MPC8544DS
• Description: BOARD DEVELOPMENT SYSTEM 8544
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8544DS

• Contents: Board
• Processor To Be Evaluated: MPC8544E
• Data Bus Width: 32 bit
• Interface Type: Ethernet, I2C
• Operating Supply Voltage: - 0.3 V to + 1.1 V
• Leaded Process Compatible: Yes
• Peak Reflow Compatible (260 C): Yes
• Rohs Compliant: Yes
• For Use With/related Products: MPC8544
• For Use With: PPC8544EVTANG - EVAL MPC8544 783FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Security Engine (SEC) 2.1
12.4.5.6
The RNG interrupt control register controls the result of detected errors. For a given error (as defined in
Section 12.4.5.5, “RNG Interrupt Status Register
set, then the error is disabled; no error interrupt occurs and the interrupt status register is not updated to
reflect the error. If the corresponding bit is not set, then upon detection of an error, the interrupt status
register is updated to reflect the error, causing assertion of the error interrupt signal, and causing the
module to halt processing.
Table 12-37
12-66
Address RNG 0x3_A038
52–55
58–61
Bits
0–50
Bits
62
63
Reset
51
56
57
62
63
W
R
0
Name
OFU
Name
—
OFU
ME
AE
—
IE
—
—
—
describes RNG interrupt status register fields.
RNG Interrupt Control Register (RNGICR)
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Table 12-36. RNG Interrupt Status Register Field Descriptions (continued)
Output FIFO underflow. The RNG output FIFO was read while empty.
0 No overflow detected
1 Output FIFO has underflowed
Reserved
Reserved
Internal error. An internal processing error was detected while generating random numbers.
0 Internal error enabled
1 Internal error disabled
Reserved
Mode error. An illegal value was detected in the mode register.
0 Mode error enabled
1 Mode error disabled
Address error. An illegal read or write address was detected within the MDEU address space.
0 Address error enabled
1 Address error disabled
Reserved
Output FIFO underflow. RNG output FIFO was read while empty.
0 Output FIFO underflow error enabled
1 Output FIFO underflow error disabled
Reserved
Table 12-37. RNG Interrupt Control Register Field Descriptions
Figure 12-45. RNG Interrupt Control Register
—
(RNGISR)”), if the corresponding bit in this register is
1000
Description
Description
50
51
IE
52
—
55
ME
56
Freescale Semiconductor
AE
57
Access: Read-only
58
—
61
OFU —
62
63