MPC8544DS Freescale Semiconductor, MPC8544DS Datasheet - Page 89
![BOARD DEVELOPMENT SYSTEM 8544](/photos/37/58/375876/mpc8544e_sml.jpg)
MPC8544DS
Manufacturer Part Number
MPC8544DS
Description
BOARD DEVELOPMENT SYSTEM 8544
Manufacturer
Freescale Semiconductor
Series
PowerQUICC III™r
Type
MPUr
Datasheets
1.MPC8544VTALF.pdf
(117 pages)
2.MPC8544VTALF.pdf
(2 pages)
3.MPC8544VTALF.pdf
(1340 pages)
4.MPC8544DS.pdf
(2 pages)
Specifications of MPC8544DS
Contents
Board
Processor To Be Evaluated
MPC8544E
Data Bus Width
32 bit
Interface Type
Ethernet, I2C
Operating Supply Voltage
- 0.3 V to + 1.1 V
Leaded Process Compatible
Yes
Peak Reflow Compatible (260 C)
Yes
Rohs Compliant
Yes
For Use With/related Products
MPC8544
For Use With
PPC8544EVTANG - EVAL MPC8544 783FCPBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
- MPC8544VTALF PDF datasheet
- MPC8544VTALF PDF datasheet #2
- MPC8544VTALF PDF datasheet #3
- MPC8544DS PDF datasheet #4
- Current page: 89 of 1340
- Download datasheet (12Mb)
About This Book
This reference manual defines the functionality of the MPC8544E. This device integrates an e500v2 core,
built on Power Architecture™ technology, with system logic required for networking,
telecommunications, and wireless infrastructure applications. The core is a low-power implementation of
resources defined by the Power ISA (instruction set architecture) for embedded processors. This book is
intended as a companion to the e500 core family reference manual.
Audience
It is assumed that the reader understands operating systems, microprocessor system design, and the basic
principles of RISC processing.
Organizations
Following is a summary and a brief description of the major parts of this reference manual:
Part I, “Overview,” describes the many features of the MPC8544E integrated host processor at an overview
level. The following chapters are included:
Part II, “e500 Core Complex and L2 Cache,” describes the many features of the device core at an overview
level and the interaction between the core complex and the L2 cache. The following chapters are included:
Freescale Semiconductor
•
•
•
•
•
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Chapter 1, “Overview,”
device, including its interfaces, and its programming model. The functional operation of the
device, with emphasis on peripheral functions is also described.
Chapter 2, “Memory Map,”
map is followed by a description of how local access windows are used to define the local address
map. The inbound and outbound address translation mechanisms used to map to and from external
memory spaces are described next. Finally, the configuration, control, and status registers are
described, including a complete listing of all memory-mapped registers with cross references to the
sections detailing descriptions of each.
Chapter 3, “Signal Descriptions,”
serve multiple functions, output signal states at reset, and reset configuration signals (and the
modes they define).
Chapter 4, “Reset, Clocking, and Initialization,”
reset (POR) sequence, power-on reset configuration, clocking, and initialization of the
MPC8544E.
Chapter 5, “Core Complex Overview,”
L1 caches and MMU that, together with the core, comprise the core complex.
Chapter 6, “Core Register Summary,”
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
provides a high-level description of features and functionality of the
describes the device memory map. An overview of the local address
lists all the external signals, cross-references for signals that
lists the e500v2 registers in reference form.
provides an overview of the e500v2 core processor and the
describes the hard and soft resets, the power-on
lxxxix
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