MPC8544DS Freescale Semiconductor, MPC8544DS Datasheet - Page 457

• Manufacturer Part Number: MPC8544DS
• Description: BOARD DEVELOPMENT SYSTEM 8544
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8544DS

• Contents: Board
• Processor To Be Evaluated: MPC8544E
• Data Bus Width: 32 bit
• Interface Type: Ethernet, I2C
• Operating Supply Voltage: - 0.3 V to + 1.1 V
• Leaded Process Compatible: Yes
• Peak Reflow Compatible (260 C): Yes
• Rohs Compliant: Yes
• For Use With/related Products: MPC8544
• For Use With: PPC8544EVTANG - EVAL MPC8544 783FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Additionally, the following three I
11.2
The following sections give an overview of signals and provide detailed signal descriptions.
11.2.1
The I
signal patterns driven on SDA represent address, data, or read/write information at different stages of the
protocol.
11.2.2
SDA and SCL, described in
devices connected to these two signals must have open-drain or open-collector outputs. The logic AND
function is performed on both of these signals with external pull-up resistors. Refer to the MPC8544E
Integrated Processor Hardware Specifications for the electrical characteristics of these signals.
Freescale Semiconductor
Signal Name
Serial Clock
(IIC n _SDA)
(IIC n _SCL)
Serial Data
•
•
•
2
C interface uses the SDA and SCL signals, described in
START condition—This condition denotes the beginning of a new data transfer (each data transfer
contains several bytes of data) and awakens all slaves.
Repeated START condition—A START condition that is generated without a STOP condition to
terminate the previous transfer.
STOP condition—The master can terminate the transfer by generating a STOP condition to free
the bus.
External Signal Descriptions
Signal Overview
Detailed Signal Descriptions
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Idle State
HIGH
HIGH
I/O
O
O
I
I
Table
When the I
to synchronize incoming data on SDA. The bus is assumed to be busy when SCL is detected
low.
As a master, the I
I
When the I
receives data from other
detected low.
When writing as a master or slave, the I
2
C module drives SCL low for data pacing.
Table 11-1. I
2
11-2, serve as a communication interconnect with other devices. All
C-specific states are defined for the I
2
2
C module is idle or acts as a slave, SCL defaults as an input. The unit uses SCL
C module is idle or in a receiving mode, SDA defaults as an input. The unit
2
C Interface Signal Descriptions
2
C module drives SCL along with SDA when transmitting. As a slave, the
I
2
C
devices on SDA. The bus is assumed to be busy when SDA is
State Meaning
2
C module drives data on SDA synchronous to SCL.
Table
11-1, for data transfer. Note that the
2
C interface:
I
2
C Interfaces
11-3