MPC8544DS Freescale Semiconductor, MPC8544DS Datasheet - Page 762

• Manufacturer Part Number: MPC8544DS
• Description: BOARD DEVELOPMENT SYSTEM 8544
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC III™r
• Type: MPUr

Specifications of MPC8544DS

• Contents: Board
• Processor To Be Evaluated: MPC8544E
• Data Bus Width: 32 bit
• Interface Type: Ethernet, I2C
• Operating Supply Voltage: - 0.3 V to + 1.1 V
• Leaded Process Compatible: Yes
• Peak Reflow Compatible (260 C): Yes
• Rohs Compliant: Yes
• For Use With/related Products: MPC8544
• For Use With: PPC8544EVTANG - EVAL MPC8544 783FCPBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Enhanced Three-Speed Ethernet Controllers
15.5.3.1.5
Figure 15-6
disable an error interruption, possibly to avoid spurious error indications external to the eTSECs.
15-30
Offset eTSEC1:0x2_4018; eTSEC3:0x2_5018
Reset
Reset
17–19
25–27
Bits
14
15
16
20
21
22
23
24
28
29
30
31
W
W
R
R
16
0
—
MMWREN
MMRDEN
GRSCEN
PERREN
XFUNEN
MAGEN
CRLEN
RXBEN
DPEEN
RXFEN
FIREN
FIQEN
Name
describes the definition for the EDIS register. The error disabled register allows the user to
1
—
—
MPC8544E PowerQUICC III Integrated Host Processor Family Reference Manual, Rev. 1
Error Disabled Register (EDIS)
BSYDIS EBERRDIS
2
Collision retry limit enable
Transmit FIFO underrun enable
Receive buffer interrupt enable
Reserved
Magic Packet received interrupt enable
MII management read completion interrupt enable
MII management write completion interrupt enable
Graceful receive stop complete interrupt enable
Receive frame interrupt enable
Reserved
Filer invalid result interrupt enable
Filed frame to invalid queue interrupt enable
Data parity error interrupt enable
Receive frame parse error enable
3
Table 15-8. IMASK Field Descriptions (continued)
Figure 15-6. EDIS Register Definition
4
—
—
6
BABTDIS — TXEDIS
7
All zeros
All zeros
8
Description
9
10
27
—
FIRDIS FIQDIS DPEDIS PERRDIS
12
28
LCDIS CRLDIS XFUNDIS
13
29
Freescale Semiconductor
Access: Read/Write
14
30
15
31