AT90CAN32 Automotive Atmel Corporation, AT90CAN32 Automotive Datasheet - Page 102

• Manufacturer Part Number: AT90CAN32 Automotive
• Manufacturer: Atmel Corporation

Specifications of AT90CAN32 Automotive

• Flash (kbytes): 32 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 53
• Ext Interrupts: 8
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Uart: 2
• Can: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 2
• Eeprom (bytes): 1024
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 125
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 4
• Output Compare Channels: 8
• Input Capture Channels: 2
• Pwm Channels: 7
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

12.5.1
12.5.2
12.5.3
102
AT90CAN32/64/128
Force Output Compare
Compare Match Blocking by TCNT0 Write
Using the Output Compare Unit
Figure 12-3
Figure 12-3. Output Compare Unit, Block Diagram
The OCR0A Register is double buffered when using any of the Pulse Width Modulation (PWM)
modes. For the normal and Clear Timer on Compare (CTC) modes of operation, the double buff-
ering is disabled. The double buffering synchronizes the update of the OCR0A Compare
Register to either top or bottom of the counting sequence. The synchronization prevents the
occurrence of odd-length, non-symmetrical PWM pulses, thereby making the output glitch-free.
The OCR0A Register access may seem complex, but this is not case. When the double buffer-
ing is enabled, the CPU has access to the OCR0A Buffer Register, and if double buffering is
disabled the CPU will access the OCR0A directly.
In non-PWM waveform generation modes, the match output of the comparator can be forced by
writing a one to the Force Output Compare (FOC0A) bit. Forcing compare match will not set the
OCF0A flag or reload/clear the timer, but the OC0A pin will be updated as if a real compare
match had occurred (the COM0A1:0 bits settings define whether the OC0A pin is set, cleared or
toggled).
All CPU write operations to the TCNT0 Register will block any compare match that occur in the
next timer clock cycle, even when the timer is stopped. This feature allows OCR0A to be initial-
ized to the same value as TCNT0 without triggering an interrupt when the Timer/Counter clock is
enabled.
Since writing TCNT0 in any mode of operation will block all compare matches for one timer clock
cycle, there are risks involved when changing TCNT0 when using the Output Compare channel,
independently of whether the Timer/Counter is running or not. If the value written to TCNT0
equals the OCR0A value, the compare match will be missed, resulting in incorrect waveform
shows a block diagram of the Output Compare unit.
bottom
FOCn
top
OCRnx
Waveform Generator
WGMn1:0
=
DATA BUS
(8-bit Comparator )
COMnX1:0
TCNTn
OCFn x (Int.Req.
OCnx
7682C–AUTO–04/08