AT90CAN32 Automotive Atmel Corporation, AT90CAN32 Automotive Datasheet - Page 421

• Manufacturer Part Number: AT90CAN32 Automotive
• Manufacturer: Atmel Corporation

Specifications of AT90CAN32 Automotive

• Flash (kbytes): 32 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 53
• Ext Interrupts: 8
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Uart: 2
• Can: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 2
• Eeprom (bytes): 1024
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 125
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 4
• Output Compare Channels: 8
• Input Capture Channels: 2
• Pwm Channels: 7
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

7682C–AUTO–04/08
CAN 2.0B
CAN 2.0A
15-bit CRC
15-bit CRC
4. CAN acknowledge error in 3-sample mode with prescaler =1
3. CAN transmission after 3-bit intermission
CRC
Field
CRC
Field
Some acknowledge errors can occur when the clock prescaler = 1 (BRP[5..0] = 0 in
CANBTR1 register) and the SMP bit is set (CANBTR3[0] = 1 in CANBTR3 register). That
can result in a reduction of the maximum length of the CAN bus.
Problem fix / workaround
If BRP[5..0]=0 use SMP=0.
If a Transmit Message Object (MOb) is enabled while the CAN bus is busy with an on going
message, the transmitter will wait for the 3-bit intermission before starting its transmission.
This is in full agreement with the CAN recommendation.
If the transmitter lost arbitration against another node, two conditions can occur:
- At least one receive MOb of the chip are programmed to accept the incoming message. In
- No receive MOb of the chip are programmed to accept the incoming message. In this case
Problem fix / workaround
Always have a receive MOb enabled ready to accept any incoming messages. Thanks to
the implementation of the CAN interface, a receive MOb must be enable at latest, before the
1
immediately after the 6th bit of the End of Frame field. This will leave in CAN2.0A mode a
minimum 19-bit time delay to respond to the end of message interrupt (RXOK) and re-
enable the receive MOb before the start of the DLC field of the next incoming message. This
minimum delay will be 39-bit time in CAN2.0B. See CAN2.0A CAN2.0B frame timings
below.
Workaround implementation
The workaround is to have the last MOb (MOb14) as "spy" enabled all the time; it is the MOb
of lowest priority. If a MOb other than MOb14 is programmed in receive mode and its accep-
tance filter matches with the incoming message ID, this MOb will take the message. MOb14
will only take messages than no other MObs will have accepted. MOb14 will need to be re-
enabled fast enough to manage back to back frames. The deadline to do this is the begin-
ning of DLC slot of incoming frames as explained above.
Minimum code to insert in CAN interrupt routine:
st
this case, the transmitter will wait for the next 3-bit intermission to retry its transmission.
the transmitter will wait for a 4-bit intermission to retry its transmission. In this case, any
other CAN nodes ready to transmit after a 3-bit intermission will start transmit before the
chip transmitter, even if their messages have lower priority IDs.
CRC
CRC
del.
del.
bit of the DLC field. The receive MOb status register is written (RXOK if message OK)
ACK
ACK
Field
ACK
Field
ACK
ACK
ACK
del.
del.
End of Frame
End of Frame
7 bits
7 bits
(RXOK)
(RXOK)
T
T
1
1
mission
mission
3 bits
3 bits
Inter-
Inter-
SOF
SOF
SOF
SOF
19-bit time minimum
11-bit base identifier
11-bit identifier
IDT28..18
ID10..0
Arbitration
Field
39-bit time minimum
SRR IDE
RTR IDE
Arbitration
Field
r0
Control
AT90CAN32/64/128
Field
T
18-bit identifier extension
2
4-bit DLC
DLC4..0
ID17..0
RTR
r1
Control
Field
r0
T
2
4-bit DLC
DLC4..0
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