AT90CAN32 Automotive Atmel Corporation, AT90CAN32 Automotive Datasheet - Page 196

• Manufacturer Part Number: AT90CAN32 Automotive
• Manufacturer: Atmel Corporation

Specifications of AT90CAN32 Automotive

• Flash (kbytes): 32 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 53
• Ext Interrupts: 8
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Uart: 2
• Can: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 2
• Eeprom (bytes): 1024
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 125
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 4
• Output Compare Channels: 8
• Input Capture Channels: 2
• Pwm Channels: 7
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

17.11.6
17.11.7
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AT90CAN32/64/128
USART1 Control and Status Register B – UCSR1B
USART0 Control and Status Register C – UCSR0C
• Bit 7 – RXCIEn: RX Complete Interrupt Enable
Writing this bit to one enables interrupt on the RXCn flag. A USARTn Receive Complete inter-
rupt will be generated only if the RXCIEn bit is written to one, the Global Interrupt Flag in SREG
is written to one and the RXCn bit in UCSRnA is set.
• Bit 6 – TXCIEn: TX Complete Interrupt Enable
Writing this bit to one enables interrupt on the TXCn flag. A USARTn Transmit Complete inter-
rupt will be generated only if the TXCIEn bit is written to one, the Global Interrupt Flag in SREG
is written to one and the TXCn bit in UCSRnA is set.
• Bit 5 – UDRIEn: USARTn Data Register Empty Interrupt Enable
Writing this bit to one enables interrupt on the UDREn flag. A Data Register Empty interrupt will
be generated only if the UDRIEn bit is written to one, the Global Interrupt Flag in SREG is written
to one and the UDREn bit in UCSRnA is set.
• Bit 4 – RXENn: Receiver Enable
Writing this bit to one enables the USARTn Receiver. The Receiver will override normal port
operation for the RxDn pin when enabled. Disabling the Receiver will flush the receive buffer
invalidating the FEn, DORn, and UPEn Flags.
• Bit 3 – TXENn: Transmitter Enable
Writing this bit to one enables the USARTn Transmitter. The Transmitter will override normal
port operation for the TxDn pin when enabled. The disabling of the Transmitter (writing TXENn
to zero) will not become effective until ongoing and pending transmissions are completed, i.e.,
when the Transmit Shift Register and Transmit Buffer Register do not contain data to be trans-
mitted. When disabled, the Transmitter will no longer override the TxDn port.
• Bit 2 – UCSZn2: Character Size
The UCSZn2 bits combined with the UCSZn1:0 bit in UCSRnC sets the number of data bits
(Character SiZe) in a frame the Receiver and Transmitter use.
• Bit 1 – RXB8n: Receive Data Bit 8
RXB8n is the ninth data bit of the received character when operating with serial frames with nine
data bits. Must be read before reading the low bits from UDRn.
• Bit 0 – TXB8n: Transmit Data Bit 8
TXB8n is the ninth data bit in the character to be transmitted when operating with serial frames
with nine data bits. Must be written before writing the low bits to UDRn.
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
RXCIE1
R/W
R
7
0
7
–
0
UMSEL0
TXCIE1
R/W
R/W
6
0
6
0
UDRIE1
UPM01
R/W
R/W
5
0
5
0
RXEN1
UPM00
R/W
R/W
4
0
4
0
USBS0
TXEN1
R/W
R/W
3
0
3
0
UCSZ12
UCSZ01
R/W
R/W
2
0
2
1
UCSZ00
RXB81
R/W
R
1
0
1
1
UCPOL0
TXB81
R/W
R/W
0
0
0
0
UCSR1B
UCSR0C
7682C–AUTO–04/08