AT90CAN32 Automotive Atmel Corporation, AT90CAN32 Automotive Datasheet - Page 154

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AT90CAN32 Automotive

Manufacturer Part Number
AT90CAN32 Automotive
Description
Manufacturer
Atmel Corporation

Specifications of AT90CAN32 Automotive

Flash (kbytes)
32 Kbytes
Pin Count
64
Max. Operating Frequency
16 MHz
Cpu
8-bit AVR
# Of Touch Channels
16
Hardware Qtouch Acquisition
No
Max I/o Pins
53
Ext Interrupts
8
Usb Speed
No
Usb Interface
No
Spi
1
Twi (i2c)
1
Uart
2
Can
1
Graphic Lcd
No
Video Decoder
No
Camera Interface
No
Adc Channels
8
Adc Resolution (bits)
10
Adc Speed (ksps)
15
Analog Comparators
1
Resistive Touch Screen
No
Temp. Sensor
No
Crypto Engine
No
Sram (kbytes)
2
Eeprom (bytes)
1024
Self Program Memory
YES
Dram Memory
No
Nand Interface
No
Picopower
No
Temp. Range (deg C)
-40 to 125
I/o Supply Class
2.7 to 5.5
Operating Voltage (vcc)
2.7 to 5.5
Fpu
No
Mpu / Mmu
no / no
Timers
4
Output Compare Channels
8
Input Capture Channels
2
Pwm Channels
7
32khz Rtc
Yes
Calibrated Rc Oscillator
Yes
14.8
154
Timer/Counter Timing Diagrams
AT90CAN32/64/128
Figure 14-8. Phase Correct PWM Mode, Timing Diagram
The Timer/Counter Overflow Flag (TOV2) is set each time the counter reaches BOTTOM. The
interrupt flag can be used to generate an interrupt each time the counter reaches the BOTTOM
value.
In phase correct PWM mode, the compare unit allows generation of PWM waveforms on the
OC2A pin. Setting the COM2A1:0 bits to two will produce a non-inverted PWM. An inverted
PWM output can be generated by setting the COM2A1:0 to three (See
The actual OC2A value will only be visible on the port pin if the data direction for the port pin is
set as output. The PWM waveform is generated by clearing (or setting) the OC2A Register at the
compare match between OCR2A and TCNT2 when the counter increments, and setting (or
clearing) the OC2A Register at compare match between OCR2A and TCNT2 when the counter
decrements. The PWM frequency for the output when using phase correct PWM can be calcu-
lated by the following equation:
The N variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024).
The extreme values for the OCR2A Register represent special cases when generating a PWM
waveform output in the phase correct PWM mode. If the OCR2A is set equal to BOTTOM, the
output will be continuously low and if set equal to MAX the output will be continuously high for
non-inverted PWM mode. For inverted PWM the output will have the opposite logic values.
The following figures show the Timer/Counter in synchronous mode, and the timer clock (clk
is therefore shown as a clock enable signal. In asynchronous mode, clk
the Timer/Counter Oscillator clock. The figures include information on when interrupt flags are
set.
count sequence close to the MAX value in all modes other than phase correct PWM mode.
Figure 14-9
TCNTn
OCnx
OCnx
Period
contains timing data for basic Timer/Counter operation. The figure shows the
1
f
OCnxPCPWM
2
=
----------------- -
N 510
f
clk_I/O
3
Table 14-4 on page
I/O
should be replaced by
OCnx Interrupt Flag S
OCRnx Update
TOVn Interrupt Flag S
(COMnx1:0 = 2)
(COMnx1:0 = 3)
7682C–AUTO–04/08
158).
T2
)

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