AT90CAN32 Automotive Atmel Corporation, AT90CAN32 Automotive Datasheet - Page 142

• Manufacturer Part Number: AT90CAN32 Automotive
• Manufacturer: Atmel Corporation

Specifications of AT90CAN32 Automotive

• Flash (kbytes): 32 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 53
• Ext Interrupts: 8
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Uart: 2
• Can: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 2
• Eeprom (bytes): 1024
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 125
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 4
• Output Compare Channels: 8
• Input Capture Channels: 2
• Pwm Channels: 7
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

13.11.15 Input Capture Register – ICR1H and ICR1L
13.11.16 Input Capture Register – ICR3H and ICR3L
13.11.17 Timer/Counter1 Interrupt Mask Register – TIMSK1
13.11.18 Timer/Counter3 Interrupt Mask Register – TIMSK3
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AT90CAN32/64/128
The Input Capture is updated with the counter (TCNTn) value each time an event occurs on the
ICPn pin (or optionally on the Analog Comparator output for Timer/Counter1). The Input Capture
can be used for defining the counter TOP value.
The Input Capture Register is 16-bit in size. To ensure that both the high and low bytes are read
simultaneously when the CPU accesses these registers, the access is performed using an 8-bit
temporary high byte register (TEMP). This temporary register is shared by all the other 16-bit
registers.
• Bit 7..6 – Reserved Bits
These bits are reserved for future use.
• Bit 5 – ICIEn: Input Capture Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Countern Input Capture interrupt is enabled. The corresponding Interrupt
Vector
• Bit 4 – Reserved Bit
This bit is reserved for future use.
• Bit 3 – OCIEnC: Output Compare C Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Countern Output Compare C Match interrupt is enabled. The corresponding
Interrupt Vector
TIFRn, is set.
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
Bit
Read/Write
Initial Value
(See “Interrupts” on page
See “Accessing 16-bit Registers” on page 116.
R/W
R/W
R
R
7
0
7
0
7
–
0
7
–
0
(See “Interrupts” on page
R/W
R/W
R
R
6
0
6
0
6
–
0
6
–
0
ICIE1
ICIE3
R/W
R/W
R/W
R/W
5
0
5
0
5
0
5
0
60.) is executed when the ICFn flag, located in TIFRn, is set.
R/W
R/W
R
R
4
0
4
0
4
–
0
4
–
0
ICR1[15:8]
ICR3[15:8]
ICR1[7:0]
ICR3[7:0]
60.) is executed when the OCFnC flag, located in
OCIE1C
OCIE3C
R/W
R/W
R/W
R/W
3
0
3
0
3
0
3
0
OCIE1B
OCIE3B
R/W
R/W
R/W
R/W
2
0
2
0
2
0
2
0
OCIE1A
OCIE3A
R/W
R/W
R/W
R/W
1
0
1
0
1
0
1
0
TOIE1
TOIE3
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
TIMSK1
TIMSK3
ICR1H
ICR3H
ICR1L
ICR3L
7682C–AUTO–04/08