AT90CAN32 Automotive Atmel Corporation, AT90CAN32 Automotive Datasheet - Page 181

• Manufacturer Part Number: AT90CAN32 Automotive
• Manufacturer: Atmel Corporation

Specifications of AT90CAN32 Automotive

• Flash (kbytes): 32 Kbytes
• Pin Count: 64
• Max. Operating Frequency: 16 MHz
• Cpu: 8-bit AVR
• # Of Touch Channels: 16
• Hardware Qtouch Acquisition: No
• Max I/o Pins: 53
• Ext Interrupts: 8
• Usb Speed: No
• Usb Interface: No
• Spi: 1
• Twi (i2c): 1
• Uart: 2
• Can: 1
• Graphic Lcd: No
• Video Decoder: No
• Camera Interface: No
• Adc Channels: 8
• Adc Resolution (bits): 10
• Adc Speed (ksps): 15
• Analog Comparators: 1
• Resistive Touch Screen: No
• Temp. Sensor: No
• Crypto Engine: No
• Sram (kbytes): 2
• Eeprom (bytes): 1024
• Self Program Memory: YES
• Dram Memory: No
• Nand Interface: No
• Picopower: No
• Temp. Range (deg C): -40 to 125
• I/o Supply Class: 2.7 to 5.5
• Operating Voltage (vcc): 2.7 to 5.5
• Fpu: No
• Mpu / Mmu: no / no
• Timers: 4
• Output Compare Channels: 8
• Input Capture Channels: 2
• Pwm Channels: 7
• 32khz Rtc: Yes
• Calibrated Rc Oscillator: Yes

17.5.2
17.6
7682C–AUTO–04/08
USART Initialization
Parity Bit Calculation
Figure 17-4. Frame Formats
The frame format used by the USARTn is set by the UCSZn2:0, UPMn1:0 and USBSn bits in
UCSRnB and UCSRnC. The Receiver and Transmitter use the same setting. Note that changing
the setting of any of these bits will corrupt all ongoing communication for both the Receiver and
Transmitter.
The USARTn Character SiZe (UCSZn2:0) bits select the number of data bits in the frame. The
USARTn Parity mode (UPMn1:0) bits enable and set the type of parity bit. The selection
between one or two stop bits is done by the USARTn Stop Bit Select (USBSn) bit. The Receiver
ignores the second stop bit. An FEn (Frame Error) will therefore only be detected in the cases
where the first stop bit is zero.
The parity bit is calculated by doing an exclusive-or of all the data bits. If odd parity is used, the
result of the exclusive or is inverted. The relation between the parity bit and data bits is as
follows:
If used, the parity bit is located between the last data bit and first stop bit of a serial frame.
The USARTn has to be initialized before any communication can take place. The initialization
process normally consists of setting the baud rate, setting frame format and enabling the Trans-
mitter or the Receiver depending on the usage. For interrupt driven USARTn operation, the
Global Interrupt Flag should be cleared (and interrupts globally disabled) when doing the
initialization.
Before doing a re-initialization with changed baud rate or frame format, be sure that there are no
ongoing transmissions during the period the registers are changed. The TXCn flag can be used
to check that the Transmitter has completed all transfers, and the RXCn flag can be used to
St
(n)
P
Sp
IDLE
P
P
d
n
even
odd
Start bit, always low.
Data bits (0 to 8).
Parity bit. Can be odd or even.
Stop bit, always high.
No transfers on the communication line (RxDn or TxDn).
An IDLE line must be high.
Parity bit using even parity
Parity bit using odd parity
Data bit n of the character
P
P
even
odd
=
=
d
d
n 1
n 1
–
–
⊕
⊕
…
…
⊕
⊕
d
d
3
3
⊕
⊕
d
d
2
2
⊕
⊕
d
d
1
1
AT90CAN32/64/128
⊕
⊕
d
d
0
0
⊕
⊕
0
1
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