cx28394 Conexant Systems, Inc., cx28394 Datasheet - Page 100

• Manufacturer Part Number: cx28394
• Description: Quad/x16/octal-t1/e1/j1 Framers
• Manufacturer: Conexant Systems, Inc.

2.0 Circuit Description
2.4 Transmitter
2-42
2.4.2.2 Circular Buffer
map. The DL1 address range is 0A4 to 0AE, and the DL2 address range is 0AF to
0B9. From this point on, the DL1 is used to describe the operation of both data
link controllers. Transmit Data Link 1 (TDL1) can be viewed as having a higher
priority than Transmit Data Link 2 (TDL2) because TDL1 overwrites the primary
rate channel after TDL2. Thus, any data that TDL2 writes to the primary rate
channel can be overwritten by TDL1, if TDL1 is configured to transmit in the
same time slot as TDL2.
TDL1 will not overwrite time slot data until it is enabled. DL1_CTL also controls
the data format and the circular buffer/FIFO mode.
link: Frame Check Sequence (FCS), non-FCS, Pack8, or Pack6. FCS and
non-FCS are HDLC-formatted messages. Pack8 and Pack6 are unformatted
messages with 8 bits per FIFO access, and 6 bits per FIFO access, respectively.
The Circular Buffer/FIFO control bit [TDL1_RPT; addr 0A6] allows the FIFO to
act as a circular buffer; in this mode, a message can be transmitted repeatedly.
This feature is available only for unformatted transmit data link applications. The
processor can repeatedly send fixed patterns on the selected channel by writing a
1- to 64-byte message into the circular buffer. The programmed message length
repeats until the processor writes a new message. The first byte of each
unformatted message is output automatically, aligned to the first frame of a
24-, or 16-frame transmit multiframe (SF/ESF/MFAS). This allows the processor
to source overhead or data elements aligned to the TX timebase. In both SF and
ESF T1 modes, unformatted messages are aligned on 24-frame boundaries.
Therefore, in SF applications the repeating message must be designed to span two
SF multiframes.
message completes transmission. Therefore, data continuity is retained during the
linkage of consecutive messages, provided that the contents of each message
consists of a multiple of the multiframe length.
DL1 and DL2 are configured identically, except for their offset in the register
The TDL1 is enabled using the DL1 Control register [DL1_CTL; addr 0A6].
The following data formats [DL1[1,0]; addr 0A6] are supported on the data
Each unformatted message written is output-aligned only after the preceding
Conexant
Quad/x16/Octal—T1/E1/J1 Framers
CX28394/28395/28398
100054E