cx28394 Conexant Systems, Inc., cx28394 Datasheet - Page 222

• Manufacturer Part Number: cx28394
• Description: Quad/x16/octal-t1/e1/j1 Framers
• Manufacturer: Conexant Systems, Inc.

3.0 Registers
3.16 System Bus Registers
TSB_CTR
TSBI[1:0]
Unused bits are reserved and should be written to 0.
OFFSET[2:0]
3-100
0D5—TSB Sync Bit Offset (TSYNC_BIT)
—
7
Force TSLIP to Center—Writing a one to TSB_CTR forces TSLIP read buffer pointer to its
initial delay condition. This can possibly force a change of transmit frame alignment if TSLIP
is configured in Elastic or Bypass modes. Writing a zero has no effect. The processor must
assert TSB_CTR after configuration of the transmit slip buffer. Afterwards, CX28398
automatically recenters TSLIP buffer according to the configured mode. Centering TSLIP
does not effect TSLIP status reported in ISR5[addr 006].
Transmit Slip Buffer Interface Mode—Selects the configuration of the TSLIP buffer. The
TSBI determines the total buffer depth and initial delay conditions. While TSLIP is bypassed,
TCKI clocks TSB input/output, and TSBCKI is ignored.
TSB Sync Bit Offset—Selects which TSB bit number coincides with TFSYNC and TMSYNC
sync pulses. Sync pulses are programmed to align to one bit in relation to TPCMI, TSIGI and
TINDO time slots. If the sync pulses are desired to coincide with location of T1 F-bit or time
slot zero Bit 1, then OFFSET is programmed to equal zero. Sync bit offset is added to time slot
offset [TSYNC_TS; addr 0D6] to form a 10-bit OFFSET value. This value applies to
TFSYNC and TMSYNC location. Both TFSYNC and TMSYNC offsets are expressed as
TSB.OFFSET, allowing the system to generate or accept sync pulses at any bit location within
the TSB frame.
—
0 = no effect
1 = force TSLIP to center
6
NOTE(S):
1. Bypass requires system bus equal to line rate.
2. Idle code and local signaling insertion apply to all modes.
TSBI
00
01
10
11
OFFSET[2:0]
Normal
Short
Elastic
Bypass
000
001
110
111
Mode
|
—
5
64 Bits
2 Frame
2 Frame
0 Bits
Depth
Total
—
4
Conexant
0.5 to 1.5 Frames
Initial Delay
32 Bits
32 Bits
0 Bits
TSYNC Location
Bit 1 or F-bit
—
3
Bit 2
Bit 7
Bit 8
|
Dependent on present depth, no
change of output frame.
Reverts to normal upon slip
Recenters automatically upon slip
TSBCKI ignored
OFFSET[2]
2
Quad/x16/Octal—T1/E1/J1 Framers
Conditions
CX28394/28395/28398
OFFSET[1]
1
OFFSET[0]
100054E
0