cx28394 Conexant Systems, Inc., cx28394 Datasheet - Page 178

• Manufacturer Part Number: cx28394
• Description: Quad/x16/octal-t1/e1/j1 Framers
• Manufacturer: Conexant Systems, Inc.

3.0 Registers
3.12 Transmitter Registers
TFRAME[3:0]
Table 3-15. E1 Transmit Framer Modes (T1/E1N = 0)
3-56
TFRAME
00XX
10XX
11XX
01XX
FAS Only
FAS + CRC
FAS + CAS
FAS + CRC + CAS
Framer Mode
Frame formatter generates Ft, Fs, FPS, FAS, MFAS, and CRC bits. Alarm formatter generates
YB2, YJ, Y0, and Y16 bits. Frame and alarm overhead formats are selected by TFRAME[3:0]
and T1/E1N settings as given in
being generated manually, automatically [TALM; addr 075], or bypassed [INS_MYEL; addr
072].
by TPCMI in bypass mode [TFRM; addr 072] or by programming TSIGn [addr 120–13F] or
TSA4–TSA8 [addr 07B–07F] buffer contents. To insert CAS, the processor selects TLOCAL
output signaling for time slot 0 and time slot 16 by programming transmit per-channel control
registers TPC0 [addr 100] and TPC16 [addr 110]. The processor then fills ABCD local
signaling value for TPC0 with MAS pattern (ABCD = 0000) and TPC16 with XYXX pattern
(ABCD = 1011).
supplied by TPCMI in bypass mode [TFRM; addr 072] or by programming TSLIP
[addr 140–17F], TDL1 [addr 0AD], or TDL2 [addr 0B8] buffer contents.
selects any SLC framer format and programs either TDL1 or TDL2. This is done in order to
operate in unformatted Pack6 mode over the F-bit channel during even frames, thus
overwriting all Fs bits inserted by frame formatter. The data pattern to be sent in 36 Fs bit
multiframe is then written as six 6-bit words to TDL1 or TDL2 circular buffer. For real-time
overhead manipulation, the processor can rewrite the circular buffer with a new 36-bit pattern
as desired.
the system bus per-channel control [SBC24; addr 0F8], then filling TSLIP buffer locations for
TS24 [addr 138, 158] with the T1DM framing pattern (TS24 = 10111YR0). If specific T1DM
elements need to be inserted and others bypassed, the processor configures TDL1 or TDL2 to
selectively insert only the desired bits. T1DM sync pattern, R-bits, and/or Y-bits. The
processor accomplishes this by programming data link bit enables [DL1_BIT; addr 0A5 or
DL2_BIT; addr 0B0].
frames [DL1_TS; addr 0A4] and Automatic Performance Report Messages [AUTO_PRM;
addr 0AA] or manually programs TDL1 to send each message.
Frame formatter does not generate CAS or Sa-bit overhead. These bits are either supplied
Frame formatter does not generate SLC, T1DM, or FDL overhead. These bits are either
To insert SLC concentrator, maintenance, alarm, and switch field values, the processor
To insert T1DM, the processor enables TIDLE insertion on time slot 24 by programming
To insert FDL, the processor configures TDL1 to operate over the F-bit channel during odd
MFAS
Ones
Ones
Yes
Yes
TS0 Overhead Insertion
Tables 3-15
Conexant
FEBE
Ones
Ones
Yes
Yes
through 3-18. Each yellow alarm is capable of
CRC4
Ones
Ones
Yes
Yes
Quad/x16/Octal—T1/E1/J1 Framers
FAS
Yes
Yes
Yes
Yes
CX28394/28395/28398
YEL
Y0
Y0
Y0
Y0
Yellow Alarms
MYEL
100054E
Y16
Y16
–
–