cx28394 Conexant Systems, Inc., cx28394 Datasheet - Page 128

• Manufacturer Part Number: cx28394
• Description: Quad/x16/octal-t1/e1/j1 Framers
• Manufacturer: Conexant Systems, Inc.

3.0 Registers
3.1 Address Map
Table 3-4. Address Map (4 of 5)
3-6
Block
Address
0E0–0FF
(Hex)
0BD
0DA
0DB
0DC
0DD
0AF
0B0
0B1
0B2
0B3
0B4
0B6
0B7
0B8
0B9
0BA
0BB
0BC
0BE
0D0
0D1
0D2
0D3
0D4
0D5
0D6
0D7
0D8
0D9
DL2_TS
DL2_BIT
DL2_CTL
RDL2_FFC
RDL2
RDL2_STAT
TDL2_FEC
TDL2_EOM
TDL2
TDL2_STAT
DL_TEST1
DL_TEST2
DL_TEST3
DL_TEST4
DL_TEST5
SBI_CR
RSB_CR
RSYNC_BIT
RSYNC_TS
TSB_CR
TSYNC_BIT
TSYNC_TS
RSIG_CR
RSYNC_FRM
SSTAT
STACK
RPHASE
TPHASE
PERR
SBCn:
n = 0 to 31
Acronym
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
W
R
R
R
R
R
R
R
R
DL2 Time-Slot Enable
DL2 Bit Enable
DL2 Control
RDL #2 FIFO Fill Control
Receive Data Link FIFO #2
RDL #2 Status
TDL #2 FIFO Empty Control
TDL #2 End Of Message Control
Transmit Data Link FIFO #2
TDL #2 Status
DLINK Test Configuration
DLINK Test Status
DLINK Test Status
DLINK Test Control #1 or Configuration #2
DLINK Test Control #2 or Configuration #2
System Bus Interface Configuration
Receive System Bus Configuration
Receive System Bus Sync Bit Offset
Receive System Bus Sync Time Slot Offset
Transmit System Bus Configuration
Transmit System Bus Sync Bit Offset
Transmit System Bus Sync Time Slot Offset
Receive Signaling Configuration
Signaling Reinsertion Frame Offset
Slip Buffer Status
Receive Signaling Stack
RSLIP Phase Status
TSLIP Phase Status
RAM Parity Status
System Bus Per-Channel Control
Conexant
Description
Quad/x16/Octal—T1/E1/J1 Framers
CX28394/28395/28398
Setting (Hex)
Register
Default
00
00
00
00
—
—
00
—
—
—
00
00
00
00
00
00
00
—
—
00
—
—
—
—
—
—
—
—
—
—
100054E