cx28394 Conexant Systems, Inc., cx28394 Datasheet - Page 4

• Manufacturer Part Number: cx28394
• Description: Quad/x16/octal-t1/e1/j1 Framers
• Manufacturer: Conexant Systems, Inc.

Detailed Feature Summary
Frame Alignment
• Framed formats:
• Maximum Average Reframe Time
• Transmitter alignment modes:
• Unframed mode
Signaling
• T1: 2-, 4-, or 16-state robbed bit
• E1: Channel Associated Signaling
• Common Channel Signaling (CCS) in
• Per-channel receive signaling stack
• Signaling state change interrupt
• Automatic and manual signaling
• Debounce signaling (2-bit
• UNICODE detection
• Signaling reinsertion on PCM system
• Separate I/O for system bus signaling
• Per-channel transparent
Loopbacks
• Remote loopback toward line
• Payload loopback
• Per-channel DS0 remote loopback
• Local loopback towards system
• Inband loopback code detection/
• Simultaneous local and remote line
Processor Interface
• Parallel 8-bit bus
• Data strobes (Motorola) or address
• Multiplexed or non-multiplexed
• Synchronous or asynchronous
• Open drain interrupt output with
100054E
– Independent transmit and receive
– T1: FT/SF/ESF/SLC/T1DM/TTC-JT(J1)
– E1: FAS/MFAS/FAS+CAS/MFAS+CAS
(MART) less than 50 ms
– Align to system bus data
– Align to system bus sync
– Align to buffer data (embedded
ABCD signaling
(CAS)
any time slot
freeze
integration)
bus
– Retains BPV transparency
– Framer digital loopback
– Per-channel DS0 local loopback
generation
loopbacks
latch enable (Intel)
address/data bus
data transfers
maskable sources
framing modes
framing)
(CX28394 and CX28398 only)
Out-of-Service Testing
and Maintenance
• Pseudo-Random Bit Sequence
• Single error insertion:
System Bus Interface (SBI)
• System bus data rates:
• Clock operation at 1x or 2x data rate
• Selectable I/O clock edges
• Master, slave, or mixed bus timing
• Bit and time slot frame sync offsets
• DS0 drop/insert indicators for
• Embedded T1 framing transport
• Receive and transmit slip buffers
• Direct connection to upper layer
• Direct connection to physical line
• Supported system bus formats:
• Separate or internally multiplexed
(PRBS):
– Independent transmit and receive
– 2
– Framed or unframed mode
– Optional 7/14 zero limit
– Bit Error Counter (BERR)
– PRBS error
– Framing error
– CRC error
– BPV/LCV error (CX28394 and
– COFA error
– 1536 kbps (T1 without F-bits)
– 1544 kbps (T1)
– 2048 kbps (E1)
– 4096 kbps (2E1)
– 8192 kbps (4E1)
external mux
per G.802
– Bypass, 2-frame, or 64-bit depth
– Slip detection with directional
– Slip buffer phase status
– Per-channel idle code insertion
– Processor accessible data buffers
devices:
– Link layer: Bt8474
– ATM layer: CN8228
interface
– CX28380
– ATT Concentration Highway
– Multi-Vendor Integration Protocol
– Mitel ST-bus
bus modes
CX28398 only)
status
Interface (CHI)
(MVIP)
11
; 2
15
Conexant
; 2
20
; 2
23
patterns
In-Service
Performance Monitoring
• One-second timer I/O to synchronize
• Receive error detectors with
• Transmit error detectors:
• Receive alarm detectors:
• Controlled Frame Slip (RFSLIP)
• Automatic and on-demand transmit
reporting
accumulators:
– Bipolar/Line Code Violations
– Excessive Zeros (EXZ)
– Loss of Frame (RLOF)
– Framing Errors (FERR)
– CRC Errors (CERR)
– Far End Block Errors (FEBE)
– Severely Errored Frames (SEF)
– Change of Frame Alignment
– Loss of Frame (TLOF)
– Framing Errors (TFERR)
– Multiframe Errors (TMERR)
– CRC Errors (TCERR)
– Loss of Transmit Clock (TLOC)
– Alarm Indication Signal (AIS)
– Loss of Signal (RLOS)
– RAI/Yellow Alarm (YEL)
– Multiframe Yellow (MYEL)
– Lost Frame Alignment (FRED)
– Lost Multiframe Alignment
– Carrier Failure Alarm (CFA) with
Uncontrolled Frame Slip (RUSLIP)
alarms:
– AIS following RLOS and/or TLOC
– Automatic AIS clock switching
– YEL following FRED
– YEL following 100ms reframe
– MYEL following MRED
– FEBE following CERR
(LCV) (CX28394 and CX28398
only)
(COFA)
(MRED)
8:1 dual slope integration
timeout