cx28394 Conexant Systems, Inc., cx28394 Datasheet - Page 228

• Manufacturer Part Number: cx28394
• Description: Quad/x16/octal-t1/e1/j1 Framers
• Manufacturer: Conexant Systems, Inc.

3.0 Registers
3.16 System Bus Registers
RSDIR
RFSLIP
RUSLIP
RDLY
3-106
Receive Slip Direction—RSDIR is updated each time an RSLIP error is latched in RFSLIP or
RUSLIP and indicates which direction the slip occurred.
Controlled RSLIP Event—RUSLIP and RFSLIP event status are latched active high when
receive slip error is detected. Either event reports RSLIP error in ISR5 [addr 006]. Active high
hold interval is defined by LATCH_ERR [addr 046]. Two types of errors are detected:
Uncontrolled RSLIP Event—See RFSLIP description.
Receive Slip Buffer Delay > 1 Frame—Indicates that real-time phase difference between
RSLIP read and write pointers is more than 192 bits (T1) or 256 bits (E1). RDLY provides a
coarse phase indicator and toggles (low) if receive clock phase advances with respect to
receive system bus clock. A finer granularity of RSLIP phase is reported in RPHASE [addr
0DB].
0 = RSLIP error deleted one frame on RPCMO or SBI resync detected
1 = RSLIP error repeated one frame on RPCMO or SBI time slot reassigned
0 = RSLIP delay less than or equal to 1 frame
1 = RSLIP delay greater than 1 frame
RSBI Mode
Normal
Bypass
Elastic
Short
1.
2.
RUSLIP
FSLIP = Controlled
RPCMO, but does not change alignment of system bus RFSYNC or
RMSYNC signals.
USLIP = Uncontrolled
both system bus data and sync outputs. RUSLIP and RFSLIP status
depends on receive system bus configuration [RSB_CR; addr 0D1].
0
0
1
0
0
1
0
1
–
RFSLIP
Conexant
0
1
0
0
1
0
0
0
–
1 frame slip on RPCMO data output. FSLIP affects
USLIP
USLIP
USLIP
RSLIP
FSLIP
FSLIP
Event
None
None
None
1 to
–
256 bit slip on RPCMO. USLIP affects
Most recent slip error direction is reported
in RSDIR.
An uncontrolled slip can occur in Normal
mode due to a resync of the SBI, or in T1
rate converted applications, the active
time slots are reassigned. The former sets
RSDIR = 0, the latter RSDIR = 1.
In short delay mode, if bus clock is faster
than receive clock, system bus will
resynchronize and USLIP is reported. If
receive clock is faster, RSLIP reverts to
Normal mode and subsequently reports
FSLIP errors.
RFSLIP is not applicable (read zero
value) while RSLIP buffer is bypassed or
configured as elastic store. FSLIP or
USLIP errors reported upon bypass mode
initialization should be ignored.
Quad/x16/Octal—T1/E1/J1 Framers
CX28394/28395/28398
Notes
100054E