cx28394 Conexant Systems, Inc., cx28394 Datasheet - Page 74

• Manufacturer Part Number: cx28394
• Description: Quad/x16/octal-t1/e1/j1 Framers
• Manufacturer: Conexant Systems, Inc.

2.0 Circuit Description
2.2 Receiver
2.2.10 Receive Data Link
2-16
2.2.10. 1 Data Link
Controllers
The RCVR contains two independent data link controllers (DL1 and DL2) and a
Bit-Oriented Protocol (BOP) transceiver. DL1 and DL2 can be programmed to
send and receive HDLC formatted messages in the Message-Oriented Protocol
(MOP) mode. Alternatively, unformatted serial data can be sent and received over
any combination of bits within a selected time slot or F-bit channel. The BOP
transceiver can preemptively receive and transmit BOP messages, such as ESF
Yellow Alarm.
DL1 and DL2 control two serial data channels operating at multiples of 4 kbps up
to the full 64 kbps time slot rate by selecting a combination of bits from odd,
even, or all frames. Both DL1 and DL2 support ESF Facilities Data Link (FDL),
SLC-96 Data Link, Sa Data Link, Common Channel Signaling (CCS), Signaling
System #7 (SS7), ISDN LAPD channels, Digital Multiplexed Interface (DMI)
Signaling in TS24, as well as the latest ETSI V.51 and V.52 signaling channels.
DL1 and DL2 each contain a 64-byte receive FIFO buffer.
the register map. The DL1 address range is 0A4 to 0AE, and the DL2 address
range is 0AF to 0B9. From this point on, DL1 is used to describe the operation of
both data link controllers.
will not function until it is enabled. DL1_CTL also controls the format of the
data. The following data formats [DL1[1:0]; addr 0A6] are supported on the data
link: Frame Check Sequence (FCS), non-FCS, Pack8, or Pack6. FCS and
non-FCS are HDLC formatted messages. Pack8 and Pack6 are unformatted
messages with 8 bits per FIFO access, or 6 bits per FIFO access, respectively (see
Table
Table 2-3. Commonly Used Data Link Settings
Enable register [DL1_TS; addr 0A4] and the DL1 Bit Enable register [DL1_BIT;
addr 0A5]. The DL1 Time Slot Enable register selects the frames and time slot to
extract the data link. The frame select tells the receiver to extract the time slot in
all frames, odd frames, or even frames. The time slot enable is a value between 0
and 31 that selects which time slot to extract. The DL1 Bit Enable register selects
which bits will be extracted in the selected time slot. Refer to
common frame, time slot, time slot bits, and modes used.
NOTE(S):
Both data link controllers are configured identically, except for their offset in
DL1 is enabled using the DL1 Control register [DL1_CTL; addr 0A6]. DL1
The time slot and bit selection are performed through the DL1 Time Slot
T1DM R Bit
ISDN LAPD
Data Link
ESF FDL
SLC-96
2-3).
Sa4
N represents any T1/E1 time slot.
Conexant
Frame
Even
Odd
Odd
All
All
Time Slot
0 (F-bits)
0 (F-bits)
24
N
1
Quad/x16/Octal—T1/E1/J1 Framers
Time Slot Bits
Don’t Care
Don’t Care
00000010
11111111
00001000
CX28394/28395/28398
Table 2-3
Mode
Pack6
for the
100054E
FCS
FCS
FCS
FCS