cx28394 Conexant Systems, Inc., cx28394 Datasheet - Page 156

• Manufacturer Part Number: cx28394
• Description: Quad/x16/octal-t1/e1/j1 Framers
• Manufacturer: Conexant Systems, Inc.

3.0 Registers
3.7 Primary Control and Status Registers
Unused bits are reserved and should be written to 0.
RSBCK
TSBCK
TXCLK[1:0]
Unused bits are reserved and should be written to 0.
RAL_CON
3-34
01A—Clock Input Mux (CMUX)
020—Receive Alarm Configuration (RAC)
—
—
7
7
RSBCK Source Select—Internal clock mux selects from one of two clock signals for
application to the RSB timebase. The RSBCKI input pin is ignored if TSBCKI is selected.
TSBCK Source Select—Internal clock mux selects from one of three clock signals for
application to the TSB timebase. If TSLIP is bypassed [TSB_CR; addr 0D4], TCKI is selected.
The TSBCKI input pin is ignored if TCKI or RSBCKI is selected.
TXCLK Source Select—Internal transmit clock mux selects from one of three clock signals.
The selected clock signal is applied to transmit clock monitor, acts as a timing reference for the
transmitter block, and must operate at the T1/E1 line rate. The selected clock signal also
appears on TCKO pin. The TCKI input pin is ignored whenever a clock source other than
TCKI is selected.
RALOS Alarm Configuration – Determines whether RALOS [ALM1; addr 047] reports loss
of receive clock (RCKI) or loss of receive signal for 1 msec.
RSBCK
—
0 = RALOS reports that RLOS [ALM1; addr 047] has been active for 1 msec
1 = RALOS reports loss of clock on RCKI pin
6
6
TXCLK[1:0]
RSBCK
TSBCK
00
01
10
0
1
0
1
x
—
—
5
5
RSBCKI pin
TSBCKI pin
TSBCKI pin
RSBCKI pin
TCKI pin
TCKI
RCKI
RSBCKI
TXCLK Source
RSBCK Source
TSBCK Source
RAL_CON
TSBCK
4
4
Conexant
Normal RSB timebase
RSB slaved to TSB
Normal TSB timebase
TSB slaved to RSB
TSLIP is bypassed
Normal transmit (With TSLIP)
Transmit slaved to receiver (Loop Timed)
Transmit slaved to RSB
—
—
3
3
Notes
Notes
Notes
—
—
2
2
Quad/x16/Octal—T1/E1/J1 Framers
CX28394/28395/28398
TXCLK[1]
—
1
1
TXCLK[0]
100054E
—
0
0