cx28394 Conexant Systems, Inc., cx28394 Datasheet - Page 53

• Manufacturer Part Number: cx28394
• Description: Quad/x16/octal-t1/e1/j1 Framers
• Manufacturer: Conexant Systems, Inc.

CX28394/28395/28398
Quad/x16/Octal—T1/E1/J1 Framers
Table 1-6. Hardware Signal Definitions (5 of 9)
100054E
TSBCKI[4:1]
TSBCKI[8:1]
TSBCKI[16:1]
TSBCKI[A]
TSBCKI[B]
TSBCKI[C]
TSBCKI[D}
TPCMI[4:1]
TPCMI[8:1]
TPCMI[16:1]
TPCMI[A]
TPCMI[B]
TPCMI[C]
TPCMI[D]
TSIGI[4:1]
TSIGI[8:1]
TSIGI[16:1]
TINDO[4:1]
TINDO[8:1]
TINDO[16:1]
TINDO[A]
TINDO[B]
TINDO[C]
TINDO[D]
TFSYNC[4:1]
TFSYNC[8:1]
TFSYNC[16:1]
TFSYNC[A]
TFSYNC[B]
TFSYNC[C]
TFSYNC[D]
Pin Label
TSB Clock Input
Bused TSB Clock
Inputs
TSB Data Input
Bused TSB Data
Input
TSB Signaling
Input
TSB Time Slot
Indicator
Bused TSB Time
Slot Indicator
TSB Frame Sync
Bused TSB
Frame Sync
Signal Name
Device
4,5,8
4,5,8
4,5,8
4,5,8
5,8
5,8
5,8
5,8
Transmit System Bus (TSB)
4
8
5
5
5
4
8
5
5
5
4
8
5
4
8
5
5
5
4
8
5
5
5
(1)
Conexant
PIO
I/O
O
I
I
I
Bit clock and I/O signal timing for TSB according to
system bus mode (see [SBI_CR; addr 0D0]). System
chooses from one of two different clocks to act as TSB
clock source (see [CMUX; addr 01A]). Rising or falling
edge clocks are independently configurable for data
signals TPCMI, TSIGI, TINDO and sync signals TFSYNC
and TMSYNC (see [TPCM_NEG and TSYN_NEG;
addr 0D4]). When configured to operate at twice the data
rate, TSB clock is internally divided by 2 before clocking
TSB data signals.
Serial data formatted into TSB frames consisting of DS0
channel time slots and optional F-bits. One group of 24
T1 time slots or 32 E1 time slots is selected from up to
four available groups; data from the group is sampled by
TSBCKI, then sent towards transmitter output. Time
slots are routed through transmit slip buffer (see
[TSLIPn; addr 140–17F]) according to TSLIP mode (see
[TSBI; addr 0D4]). F-bits are taken from the start of each
TSB frame or from within an embedded time slot (see
[EMBED; addr 0D0]) and optionally inserted into the
transmitter output (see [TFRM; addr 072] register).
Serial data formatted into TSB frames containing ABCD
signaling bits for each system bus time slot. Four bits of
TSIGI time slot carry signaling state for each
accompanying TPCMI time slot. Signaling state of every
time slot is sampled during first frame of the TSB
multiframe and then transferred into transmit signaling
buffer [TSIGn; addr 120–13F].
Active-high output pulse marks selective transmit
system bus time slots as programmed by SBCn [addr
0E0-0FF], TINDO occurs on TSBCKI rising or falling
edges as selected by TPCM_NEG (see [TSBI; addr 0D4]).
Input or output TSB frame sync (see [TFSYNC_IO; addr
018]). TFSYNC output is active high for one TSB clock
cycle at programmed offset bit location (see
[TSYNC_BIT; addr 0D5]), marking offset bit position
within each TSB frame and repeating once every 125 s.
When transmit framer is also enabled, TSB timebase and
TFSYNC output frame alignment are established by
transmit framer's examination of TPCMI serial data
input. When TFSYNC is programmed as an input, the
low-to-high signal transition is detected and is used to
align TSB timebase to programmed offset bit value. TSB
timebase flywheels at 125 s frame interval after the last
TFSYNC is applied.
Definition
1.0 Product Description
1.2 Pin Assignments
1-35