cx28394 Conexant Systems, Inc., cx28394 Datasheet - Page 137

• Manufacturer Part Number: cx28394
• Description: Quad/x16/octal-t1/e1/j1 Framers
• Manufacturer: Conexant Systems, Inc.

CX28394/28395/28398
Quad/x16/Octal—T1/E1/J1 Framers
3.5 Interrupt Status Registers
An Interrupt Status Register (ISR) bit is latched active (high) whenever its corresponding interrupt source
reports an interrupt event. The processor reads ISR to clear all latched ISR bits. If the corresponding interrupt
enable is active (high), each interrupt event forces the associated IRR bit active (high). Interrupt sources fall into
two categories:
is active (high). Otherwise, the interrupt status is latched and reported according to the selected latching mode
[LATCH; addr 046] without asserting the MIR bit or the INTR* output pin.
status registers.
Table 3-6. Interrupt Status Register Summary
100054E
Bit
• Rising-edge source reports an interrupt event when status changes from inactive to active state. Unless
• Dual-edge source reports an interrupt event when status changes from inactive to active (rising edge), or
Interrupt events are reported in real time in the MIR register and on the INTR* output pin if interrupt enable
0
1
2
3
4
5
6
7
specifically noted otherwise, all ISR bits are rising-edge sources.
from active to inactive (falling edge). The processor must read the associated real-time status to determine
which edge occurred.
ALARM1
SIGFRZ
RALOS
RMYEL
RPDV
RLOF
RLOS
ISR7
RYEL
RAIS
004
ALARM2
LOOPUP
LOOPDN
ONESEC
TLOC
TPDV
ISR6
TLOF
005
—
—
ERROR
MERR
RSLIP
TSLIP
SERR
CERR
FERR
ISR5
006
—
—
BERR[12]
FERR[12]
FEBE[10]
CRC[10]
LCV[16]
COFA[2]
FRED[4]
COUNT
Conexant
SEF[2]
ISR4
007
RMSYNC
RFRAME
TMSYNC
TFRAME
TIMER
ISR3
RSIG
RMF
TSIG
TMF
008
TEMPTY
Table 3-6
TDLERR
RNEAR
TNEAR
RFULL
RMSG
TMSG
TBOP
ISR2
DL1
009
3.5 Interrupt Status Registers
summarizes the interrupt
TEMPTY
TDLERR
RNEAR
TNEAR
RFULL
RMSG
TMSG
RBOP
ISR1
00A
DL2
3.0 Registers
TMERR
PSYNC
TSERR
TCERR
TFERR
BSLIP
PATT
ISR0
00B
—
—
3-15