cx28394 Conexant Systems, Inc., cx28394 Datasheet - Page 234

• Manufacturer Part Number: cx28394
• Description: Quad/x16/octal-t1/e1/j1 Framers
• Manufacturer: Conexant Systems, Inc.

3.0 Registers
3.16 System Bus Registers
Transmit signaling from the TSIGI pin is automatically placed into the TSIGn buffer. Processor controls TSIGn
insertion into the transmitter output by selecting TSIGO[inTPCn]. The processor can read monitor TSIGn from
system supplied signaling or can use TSIGn for inter-processor communication. During E1 modes, TSIG0 and
TSIG16 buffer locations hold the CAS multiframe alignment signal (MAS.1 through MAS.4), Extra bits (X.1
through X.4), and multiframe yellow alarm (MYEL) bits supplied from TSIGI.
TSIGn.3.
TSIGn.2.
TSIGn.1.
TSIGn.0.
TPCM[1]
TPCM[2]
TPCM[3]
TPCM[4]
TPCM[5]
TPCM[6]
TPCM[7]
TPCM[8]
3-112
120–13F—Transmit Signaling Buffer (TSIGn; n = 0 to 31)
140–15F—Transmit PCM Slip Buffer (TSLIP_LOn; n = 0 to 31)
Unused bits are reserved and should be written to 0.
TPCM[1]
—
7
7
Input Signaling A Bit
Input Signaling B Bit
Input Signaling C Bit
Input Signaling D Bit
First bit
Second bit
Third bit
Fourth bit
Fifth bit
Sixth bit
Seventh bit
Eighth bit received on TPCMI
TPCM[2]
—
6
6
TPCM[3]
—
5
5
TSIG0 (E1)
MAS.1
MAS.2
MAS.3
MAS.4
TPCM[4]
—
4
4
Conexant
TSIGn[3]
TPCM[5]
TSIG16 (E1)
X.1
MYEL
X.3
X.4
3
3
TSIGn[2]
TPCM[6]
2
2
Quad/x16/Octal—T1/E1/J1 Framers
CX28394/28395/28398
TSIGn[1]
TPCM[7]
1
1
TSIGn[0]
TPCM[8]
100054E
0
0