cx28394 Conexant Systems, Inc., cx28394 Datasheet - Page 207

• Manufacturer Part Number: cx28394
• Description: Quad/x16/octal-t1/e1/j1 Framers
• Manufacturer: Conexant Systems, Inc.

CX28394/28395/28398
Quad/x16/Octal—T1/E1/J1 Framers
DL2_TS[4:0]
DL2_BIT[7:0]
Unused bits are reserved and should be written to 0.
TDL2_RPT
100054E
0B0—DL2 Bit Enable (DL2_BIT)
0B1—DL2 Control (DL2_CTL)
DL2_BIT[7]
—
7
7
DL2_BIT[6]
Time Slot Word Enable—Transmit and receive data link 2 operates on data only during the
specified time slot. During T1 mode, selecting time slot zero enables data link operation on the
F-bit positions.
DL2 Bit Select—Works in conjunction with DL2_TS [addr 0AF] to select one or more time
slot bits for data link input and output. Any combination of bits may be enabled by writing the
corresponding DL2_BIT active (high). The LSB enables the first bit transmitted or received,
and MSB enables eighth bit transmitted or received. DL2_BIT has no effect when DL2_TS
selects T1 F-bits.
Circular Transmit Buffer Enable—Processor can fill transmit FIFO [TDL2; addr 0B8] with up
to 64 bytes (Pack6 or Pack8 bits/byte) of unformatted data to be sent repeatedly. While
TDL2_RPT is active high, data written to TDL2 is held until the processor writes an end of
message [TDL2_EOM; addr 0B7]. After TDL2_EOM is written, the transmitter waits for the
beginning of the next output multiframe (based on the selected transmit framing mode) before
sending the first byte of the circular buffer. Subsequent bytes are output in the selected time
slot/overhead bits and will continue to wrap around (recirculate) from the buffer until the
processor writes new buffer data and another TDL2_EOM. This allows the processor to send
multiframe aligned data patterns in ESF, SF, SLC, FAS, MFAS, or CAS overhead bits.
—
0 = disable data link bit
1 = enable data link bit
0 = normal transmit FIFO
1 = enable circular transmit buffer
6
6
DL2_TS[4:0]
00000
00001
11110
11111
|
DL2_BIT[5]
—
5
5
F-bit (T1) or TS0 (E1)
DL2_BIT[4]
TDL2_RPT
Time Slot Enable
4
4
Conexant
TS30
TS31
TS1
|
DL2_BIT[3]
DL2[1]
3
3
DL2_BIT[2]
DL2[0]
2
2
DL2_BIT[1]
TDL2_EN
3.15 Data Link Registers
1
1
3.0 Registers
DL2_BIT[0]
RDL2_EN
0
0
3-85