cx28394 Conexant Systems, Inc., cx28394 Datasheet - Page 89

• Manufacturer Part Number: cx28394
• Description: Quad/x16/octal-t1/e1/j1 Framers
• Manufacturer: Conexant Systems, Inc.

CX28394/28395/28398
Quad/x16/Octal—T1/E1/J1 Framers
Figure 2-14. G.802 Embedded Framing
100054E
2.3.4.4 Signaling Stack
NOTE(S):
(1)
(2)
(3)
(4)
(5)
X = unused bits
u = unassigned time slot (see ASSIGN bit [addr 0E0 to 0FF])
F
F
F
2.3.4.5 Embedded
A
B
C
= T1 frame bit, frame A
= T1 frame bit, frame B
= T1 frame bit, frame C
RPCMO
RNRZ
Framing
E1 Framing
Time Slot
F
u
0
A
1
1
The Receive Signaling Stack (RSTACK) allows the processor to quickly extract
signaling changes without polling every channel. RSTACK is activated on a
per-channel basis by setting the Received Signaling Stack (SIG_STK) control bit
in the Receive Per-Channel Control register [RPC0 to RPC31; addr 180 to 19F].
The signaling stack stores the channel and the A, B, C, and D signaling bits that
changed in the last multiframe. The stack has the capacity to store signaling
changes for all 24 (T1) or 30 (E1) PCM channels.
changed, an interrupt occurs with RSIG set in the Timer Interrupt Status register
[ISR3; addr 008]. The processor then reads the Receive Signaling Stack [STACK;
addr 0DA] twice to retrieve the channel number (WORD = 0) and the new ABCD
value (WORD = 1), and continues to read from STACK until the MORE bit in
STACK is cleared, indicating the RSIG stack is empty.
occur at each multiframe boundary in T1 modes, regardless of signaling change.
This mode provides an interrupt aligned to the multiframe to read the RSIG
buffer, rather than to read RSTACK.
Embedded framing mode bit (EMBED; addr 0D0) instructs the RSB to embed
framing bits in RPCMO while in T1 mode.
describes how 24 T1 time slots and one framing bit (193 bits) are mapped to 32
E1 time slots (256 bits). This mapping is done by leaving TS0 and TS16
unassigned; by storing the 24 T1 time slots in TS1 to TS15, and TS17 to TS25;
and by storing the frame bit in bit 1 of TS26 (see
TS31 are also unassigned.
2
2
At the end of any multiframe where one or more ABCD signaling values have
Optionally, the processor can select RSIG interrupt (SET_RSIG; addr 0D7) to
The Embedded mode supports ITU-T Recommendation G.802, which
Frame A
E1 Multiframe/Signalling
14
14
Time Slot
15 16 17
15
16 17 18
u
Conexant
F
B
23
X
24 F
24
X
25
B
X
26 27
1
X
u
2
X
u
Frame B
X
31
u
Figure
X
23 24
0
1
2-14). TS26 through
F
2
C
2.0 Circuit Description
1
2
2.3 System Bus
2-31