cx28394 Conexant Systems, Inc., cx28394 Datasheet - Page 54

• Manufacturer Part Number: cx28394
• Description: Quad/x16/octal-t1/e1/j1 Framers
• Manufacturer: Conexant Systems, Inc.

1.0 Product Description
1.2 Pin Assignments
Table 1-6. Hardware Signal Definitions (6 of 9)
1-36
TMSYNC[4:1]
TMSYNC[8:1]
TMSYNC[16:1]
RSBCKI[4:1]
RSBCKI[8:1]
RSBCKI[16:1]
RSBCKI[A]
RSBCKI[B]}
RSBCKI[C]}
RSBCKI[D]}
RPCMO[4:1]
RPCMO[8:1]
RPCMO[16:1]
RPCMO[A]
RPCMO[B]
RPCMO[C]
RPCMO[D]
RINDO[4:1]
RINDO[8:1]
RINDO[A]
RINDO[B]
RINDO[C]
RINDO[D]
Pin Label
TSB Multiframe
Sync
RSB Clock Input
Bused RSB Data
Input
RSB Data Output
Bused RSB Data
Output
RSB Time Slot
Indicator
Bused RSB Time
Slot Indicator
Signal Name
Transmit System Bus (TSB) (Continued)
Device
4,5,8
4,5,8
4,5,8
5,8
5,8
5,8
Receive Systetm Bus (RSB)
4
8
5
4
8
5
5
5
4
8
5
5
5
4
8
5
5
(1)
Conexant
PIO
I/O
O
O
I
Input or output TSB multiframe sync (see [TMSYNC_IO;
addr 018]). TMSYNC output is active high for one TSB
clock cycle at programmed offset bit location (see
[TSYNC_BIT; addr 0D5]), marking offset bit position
within each TSB multiframe and repeating once every 6
ms coincident with TFSYNC. When transmit framer is
also enabled, TSB timebase and TMSYNC output
multiframe alignment are established by transmit
framer's examination of TPCMI serial data input. When
TMSYNC is programmed as an input, the low-to-high
signal transition is detected and is used to align TSB
timebase to programmed offset bit value and first frame
of the multiframe. TSB timebase flywheels at 6 ms
multiframe intervals after the last TMSYNC is applied. If
system bus applies TMSYNC input, TFSYNC input is not
needed.
Bit clock and I/O signal timing for RSB according to
system bus mode (see [SBI_CR; addr 0D0]). System
chooses from one of two different clocks to act as RSB
clock source (see [CMUX; addr 01A]). Rising or falling
edge clocks are independently configurable for data
signals RPCMO, RSIGO, RINDO and sync signals
RFSYNC, RMSYNC (see [RPCM_NEG and RSYN_NEG;
addr 0D1]). When configured to operate at twice the data
rate, RSB clock is internally divided by 2 before clocking
RSB data signals.
Serial data formatted into RSB frames consisting of DS0
channel time slots, optional F-bits and optional ABCD
signaling. Time slots are routed through receive slip
buffer (see [RSLIPn; addr 1C0–1FF]) according to RSLIP
mode (see [RSBI; addr 0D1]). Data for each output time
slot is assigned sequentially from received time slot data
according to system bus channel programming (see
[ASSIGN; addr 0E0–0FF]). F-bits are output at the start
of each RSB frame or at the embedded time slot location
(see [EMBED; addr 0D0]). ABCD signaling is optionally
inserted on a per-channel basis (see [INSERT;
addr 0E0–0FF]) from the local signaling buffer (see
[RLOCAL; addr 180–19F]) or from the receive signaling
buffer [RSIGn; addr 1A0–1BF]. When enabled, robbed
bit signaling or CAS reinsertion is performed according
to T1/E1 mode: The eighth time slot bit of every sixth T1
frame is replaced, or the 4-bit signaling value in the E1
time slot 16 is replaced.
Active high output pulse marks selective receive system
bus time slots as programmed by SBCn [addr 0E0-0FF].
RINDO occurs on RSBCKI rising or falling edges as
selected by RPCM_NEG (see [RSBI; addr 0D1]). Only
available in Multiplexed System Bus mode on CX28395
(see [FCR; addr 080]).
Quad/x16/Octal—T1/E1/J1 Framers
Definition
CX28394/28395/28398
100054E