cx28394 Conexant Systems, Inc., cx28394 Datasheet - Page 130

• Manufacturer Part Number: cx28394
• Description: Quad/x16/octal-t1/e1/j1 Framers
• Manufacturer: Conexant Systems, Inc.

3.0 Registers
3.2 Global Control and Status Registers
3.2 Global Control and Status Registers
Global registers are applicable to all framers in the CX28394 and CX28398. There are two sets of global
registers for the CX28395, one for each 8-framer group.
Read only value.
DID[7:4]
DID[3:0]
Unused bits are reserved and should be written to 0.
GRESET
ONESEC_IO
3-8
000—Device Identification (DID)
080—Framer Control Register (FCR)
GRESET
DID[7]
7
7
Device Revision—A value of 0x4 indicates the current revision.
Device ID—A value of 0x8 indicates the CX28398 or CX28395. A value of 0x4 indicates the
CX28394.
Global Reset —When written to 1 by the microprocessor, GRESET initiates an internal global
reset process which initializes all global control registers and certain control registers for all
framers to their default settings (see
15 sec.
GRESET remains active (1) during the reset process to allow the microprocessor to detect
reset completion. GRESET also indicates a reset operation triggered by power-up or by an
active low RST* pin. After GRESET initialization, the following is true:
Bidirectional ONESEC Input/Output Mode—Selects input or output mode for ONESEC
signal pin and controls the internal timer interval used for one-second status latching [LATCH;
addr 046]. When ONESEC is an output, SYSCLK is used to develop the one-second timer
interval output with an arbitrarily defined initial starting location. When ONESEC is an input,
the timer/latch interval is aligned to rising edge of ONESEC input. The system can apply
ONESEC input to define any length timer/latch interval up to 1 second, but not greater than 1
second.
DID[6]
The processor must not write to the control registers until the reset process is complete.
• System bus outputs (RSIGO, RPCMO, and SIGFRZ) for all framers are three-stated.
• Programmable I/O pins are configured as inputs.
• Global control and framer control registers are set to their default values.
0 = ONESEC input
1 = ONESEC output
6
6
–
DID[5]
5
5
–
DID[4]
4
4
–
Conexant
Table
3-4). The internal reset process takes a maximum of
DID[3]
3
3
–
ONESEC_IO
DID[2]
2
2
Quad/x16/Octal—T1/E1/J1 Framers
CX28394/28395/28398
SBIMODE[1]
DID[1]
1
1
SBIMODE[0]
DID[0]
100054E
0
0