cx28394 Conexant Systems, Inc., cx28394 Datasheet - Page 203

• Manufacturer Part Number: cx28394
• Description: Quad/x16/octal-t1/e1/j1 Framers
• Manufacturer: Conexant Systems, Inc.

CX28394/28395/28398
Quad/x16/Octal—T1/E1/J1 Framers
RFULL1
AUTO_PRM
PRM_CR
PRM_R
PRM_U1
PRM_U2
PRM_SL
100054E
0AA—Performance Report Message (PRM)
AUTO_PRM
7
Receive FIFO Full—Indicates data link has completely filled 64 byte locations in the receive
FIFO. In all cases, RFULL1 is an error, indicating the processor didn’t keep pace with the
receiver and indicates one or more received messages were discarded after the FIFO became
full. The FIFO may still contain one or more Good received messages, and the processor may
still process all receive FIFO contents as usual. However, any message that was in progress
when FIFO reached full is discarded and is also reported with Partial end of message status
and a zero byte count (which distinguishes a full end of message status from a normal abort or
error message status).
Automatic PRM Insertion—AUTO_PRM instructs the data link transmitter to format and send
a Performance Report Message on the selected transmit channel after each occurrence of the
ONESEC interrupt. To meet PRM requirements specified in ANSI T1.403-1995, FCS mode
[DL1_CTL; addr 0A6] and one second error count latching [LATCH_CNT; addr 046] must
both be enabled. In addition, the data link channel must be selected to output on Facility Data
Link (FDL) framing bits [DL1_TS=0x40; addr 0A4]. Octets 1-14 of the transmit PRM
message contents are automatically encoded as shown in
Message
and FRED errors [addr 050-05A]. RFSLIP errors [SSTAT; addr 0D9] are also automatically
encoded if AUTO_SL (described below) is enabled. The remaining PRM message contents
typically remain fixed and are supplied by the processor from other bits that follow in the PRM
register. Note that BOP priority codeword transmissions are interrupted by AUTO_PRM if
TDL1 is granted output priority [TBOP_MODE=11; addr 0A0]. Note also that AUTO_PRM
messages take up no space in the transmit data link FIFO, but are inserted on the transmit
channel only after the FIFO is empty. Therefore, if the processor needs to transmit another type
of FDL message between PRM messages, the processor must write that message after
AUTO_PRM has begun sending (i.e. after ONESEC interrupt).
Transmit CR Message Bit—The processor writes the selected C/R bit value to send in each
PRM.
Transmit R Message Bit—The processor writes the selected R bit value to send in each PRM.
Transmit U1 Message Bit—The processor writes the selected U1 bit value to send in each
PRM.
Transmit U2 Message Bit—The processor writes the selected U2 bit value to send in each
PRM.
Transmit SL Message Bit—The processor writes the selected SL bit value to send in each
PRM.
PRM_CR
0 = FIFO is less than full
1 = FIFO has been completely filled
0 = no automatic PRM
1 = send PRM automatically every ONESEC
6
Structure. The encodings are based on the number of received CRC, FPS, LCV , SEF
PRM_R
5
PRM_U1
4
Conexant
PRM_U2
3
PRM_SL
Table A-5, Performance Report
2
AUTO_SL
3.15 Data Link Registers
1
3.0 Registers
SEND_PRM
0
3-81