cx28394 Conexant Systems, Inc., cx28394 Datasheet - Page 55

• Manufacturer Part Number: cx28394
• Description: Quad/x16/octal-t1/e1/j1 Framers
• Manufacturer: Conexant Systems, Inc.

CX28394/28395/28398
Quad/x16/Octal—T1/E1/J1 Framers
Table 1-6. Hardware Signal Definitions (7 of 9)
100054E
RSIGO[4:1]
RSIGO[8:1]
RSIGO[16:1]
RFSYNC[4:1]
RFSYNC[8:1]
RFSYNC[16:1]
RFSYNC[A]
RFSYNC[B]
RFSYNC[C]
RFSYNC[D]
RMSYNC[4:1]
RMSYNC[8:1]
RMSYNC[16:1]
SIGFRZ[4:1]
SIGFRZ[8:1]
Pin Label
RSB Signaling
Output
RSB Frame Sync
Bused RSB
Frame Sync
RSB Multiframe
Sync
Signaling Freeze
Signal Name
Receive Systetm Bus (RSB) (Continued)
Device
4,8,5
5,8
4
8
5
4
8
5
5
5
4
8
5
4
8
(1)
Conexant
PIO
PIO
I/O
O
O
Serial data formatted into RSB frames consisting of
ABCD signaling bits for each system bus time slot. Four
bits of RSIGO time slot carry signaling state for each
accompanying RPCMO time slot. Local or through
signaling bits are output in every frame for each time slot
and updated once per RSB multiframe, regardless of
per-channel RPCMO signaling reinsertion.
Input or output RSB frame sync (see [RFSYNC_IO;
addr 018]). RFSYNC output is active high for one RSB
clock cycle at programmed offset bit location (see
[RSYNC_BIT; addr 0D2]), marking offset bit within each
RSB frame and repeating once every 125 s. RSB
timebase and RFSYNC output frame alignment begins at
an arbitrary position and changes alignment according to
RSLIP mode (see [RSBI; addr 0D1]). When RFSYNC is
programmed as an input, the low-to-high signal
transition is detected and used to align RSB timebase to
the programmed offset. RSB timebase flywheels at
125 s frame interval after the last RFSYNC is applied.
Input or output RSB multiframe sync (see [RMSYNC_IO;
addr 018]). RMSYNC output is active high for one RSB
clock cycle at programmed offset bit location (see
[RSYNC_BIT; addr 0D2]), marking offset bit within each
RSB multiframe and repeating once every 6 ms
coincident with RFSYNC. RSB timebase and RMSYNC
output multiframe alignment begins at an arbitrary
position and changes alignment according to RSLIP
mode (see [RSBI; addr 0D1]). When RMSYNC is
programmed as an input, the low-to-high signal
transition is detected and is used to align the RSB
timebase to programmed offset and first frame of the
multiframe. RSB timebase flywheels at 6 ms multiframe
interval after the last RMSYNC is applied.
Active high indicates that signaling bit updates are
suspended for both receive signaling buffer [RSIGn;
addr 1A0–1BF] and stack [STACK; addr 0DA] register.
SIGFRZ is clocked by RSB clock, goes high coincident
with receive loss of frame alignment (see RLOF;
addr 047) and returns low 6–9 ms after recovery of
frame alignment.
Definition
1.0 Product Description
1.2 Pin Assignments
1-37