cx28394 Conexant Systems, Inc., cx28394 Datasheet - Page 142

• Manufacturer Part Number: cx28394
• Description: Quad/x16/octal-t1/e1/j1 Framers
• Manufacturer: Conexant Systems, Inc.

3.0 Registers
3.5 Interrupt Status Registers
RSIG
RMSYNC
RMF
RFRAME
All events in ISR2 are from rising edge sources. Each event is latched active high and held until the processor
read clears ISR2. Each event triggers an interrupt if the corresponding IER2 bit is enabled [addr 011].
TBOP
RFULL1
RNEAR1
RMSG1
TDLERR1
TEMPTY1
TNEAR1
TMSG1
3-20
009—Data Link 1 Interrupt Status (ISR2)
TBOP
7
Receive Signaling Stack—Indicates that one or more signaling bit changes were detected
during the prior receive multiframe, and that new ABCD (robbed bit or CAS) signaling is
available on the Receive Signaling Stack Register [addr 0DA]. RSIG is cleared by processor
read of ISR3, independent of STACK contents.
Receive System Bus MF Sync—Activated every 3 ms (SF/SLC/ESF), or 2 ms (CAS)
coincident with the first bit of receive system bus multiframe output on RPCMO.
Receive Multiframe Boundary—RMF is activated every 1.5 ms (SF/SLC), 3 ms (ESF), or
2 ms (MFAS) coincident with the first bit of a received multiframe. If MAS is not included in
the receive framer criteria, then RMF is activated at 2 ms interval.
Receive Frame Boundary—Activated every 193 bits (T1) or 256 bits (E1) coincident with the
first bit of a received frame. Processor may read RPHASE [addr 0DB] to determine which
RSLIP buffer half can be accessed.
BOP Codeword Transmitted
and a new TBOP value can be written [TBOP; addr 0A1].
Receive FIFO Full
write received data to a full FIFO causing the receive data link FIFO to overrun. In
unformatted modes (Pack6 and Pack8), RFULL is set when the receive FIFO is filled to the
MSG_FILL Limit selected in register RDL1_FFC [addr 0A7].
Receive FIFO Near Full
selected in register RDL1_FFC [addr 0A7].
Message Received
available in the receiver FIFO.
Transmit FIFO Error
the FIFO without encountering an end of message [TDL1_EOM; addr 0AC]. The underrun
condition also forces transmission of an HDLC abort code.
Transmit FIFO Empty
write to a full FIFO. Overflow data is ignored by the transmit FIFO.
Transmit FIFO Near Empty
selected in register TDL1_FEC [addr 0AB].
Message Transmitted
is just beginning transmission.
RFULL1
0 = no stack update
1 = new ABCD signaling
0 = no timer event
1 = RSB multiframe
0 = no timer event
1 = receive multiframe
0 = no timer event
1 = receive frame
6
RNEAR1
5
—
—
Set when a complete message or a partial message is received and
In HDLC modes, RFULL is set when the data link receiver attempts to
—
—
—
Set when the FIFO underruns as a result of the internal logic emptying
Set when a complete message has been transmitted and the closing flag
—
Set when the FIFO overflows as a result of the processor attempting to
Set when the receive FIFO fill level reaches the near full threshold
—
—
RMSG1
Set when a valid Bit Oriented Codeword has been transmitted
Set when the transmit FIFO level falls below the threshold
4
Conexant
TDLERR1
3
TEMPTY1
2
Quad/x16/Octal—T1/E1/J1 Framers
CX28394/28395/28398
TNEAR1
1
TMSG1
100054E
0