cx28394 Conexant Systems, Inc., cx28394 Datasheet - Page 210

• Manufacturer Part Number: cx28394
• Description: Quad/x16/octal-t1/e1/j1 Framers
• Manufacturer: Conexant Systems, Inc.

3.0 Registers
3.15 Data Link Registers
Two different read byte values are supplied: WORD0 equals message status, and WORD1 equals message data.
The processor determines which byte value is located in the FIFO by first reading the receiver data link status
[RDL2_STAT; addr 0B4]. In some cases, multiple consecutive status bytes may be placed in the FIFO. Thus, the
processor must always read RDL2_STAT before reading RDL2 to distinguish between WORD0 and WORD1
byte values. However, each time a non-zero byte count [RDL2_CNT] status is read, the processor is guaranteed
the next RDL2_CNT reads from RDL2 will equal message data [WORD1] and not message status. A status
byte occupies 1 byte of FIFO space, just the same as a message data byte occupies 1 byte of FIFO space.
EOM[1, 0]
RDL2_CNT[5:0]
RDL2[7:0]
3-88
WORD0: Message Status
WORD1: Message Data
0B3—Receive Data Link FIFO #2 (RDL2)
RDL2[7]
EOM[1]
7
7
End of Message—The receive data link reports an End of Message status for each occurrence
of a complete (Good), a continued (Partial), an errored (FCS/Non-integer), or an aborted
(Abort) message. Note that properly received unformatted messages are reported with a Partial
end of message status. The processor responds to Good or Partial status by reading the
indicated number of data bytes [RDL2_CNT] from RDL2. For abort or error cases,
RDL2_CNT equals zero to indicate all received data from that message was discarded. Note
that a Good status with RDL2_CNT=0 is reported if the processor reads RDL2 while the
receiver is in progress of filling the FIFO (in which case RDL2_STAT contains RSTAT2=1
and RMSG2=1). If an abort or error status with zero byte count is reported after the processor
has already buffered a prior HDLC Partial message, that partial buffered processor data should
be discarded. Abort status is reported if the receiver detects a string of 7 or more consecutive
ones during an HDLC message. FCS error status is reported if FCS mode is enabled, and the
checksum calculated over the received HDLC message does not match the received 16-bit
FCS. Non-integer error status is reported if the receiver detects a closing FLAG character
yielding an HDLC message length which is not an integer number of 8-bit octets.
Byte Count [5:0]—Indicates the number of Message Data [WORD1] bytes that are stored in
subsequent consecutive FIFO locations, constituting one received message. The reported byte
count is the actual number of bytes in the range of 0 to 63 bytes, where 0 indicates for the
processor to read. The processor can either read the specified number of message data bytes
consecutively from RDL2 or can poll RDL2_STAT after reading each data byte until
RDL2_STAT reports an end of message (i.e. RMPTY2=1 or RSTAT2=1).
Receive Message Data—Filled by the receiver data link, from LSB to MSB, with bits from the
selected channel. The processor reads 8-bit FIFO data during HDLC and Pack8 modes. During
Pack6 mode, only the six least significant bits RDL2[5:0] are filled.
RDL2[6]
EOM[0]
00 = Good
01 = FCS/Non-integer
10 = Abort
11 = Partial
6
6
RDL2_CNT[5]
RDL2[5]
5
5
RDL2_CNT[4]
RDL2[4]
4
4
Conexant
RDL2_CNT[3]
RDL2[3]
3
3
RDL2_CNT[2]
RDL2[2]
2
2
Quad/x16/Octal—T1/E1/J1 Framers
CX28394/28395/28398
RDL2_CNT[1]
RDL2[1]
1
1
RDL2_CNT[0]
RDL2[0]
100054E
0
0