cx28394 Conexant Systems, Inc., cx28394 Datasheet - Page 131
cx28394
Manufacturer Part Number
cx28394
Description
Quad/x16/octal-t1/e1/j1 Framers
Manufacturer
Conexant Systems, Inc.
Datasheet
1.CX28394.pdf
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CX28394/28395/28398
Quad/x16/Octal—T1/E1/J1 Framers
SBIMODE[1:0]
CX28394
CX28398 and CX28395
MIR[7:0]
100054E
081—Master Interrupt Request (MIR)
MIR[7]
—
7
7
The processor writes FCR at power-up to configure the system bus interface mode. Each
group of four framers can be configured as separate system bus interfaces or as an internally
multiplexed group. The group consisting of framers 1 through 4 (9 through 12) can be
configured to share a common system bus interface, SBI Bus A. The group consisting of
framers 5 through 8 (13 through 16) can also be configured to share a common system bus
interface, SBI Bus B.
An active MIR bit indicates which framer has active interrupts. An MIR bit is latched active
(high) whenever any bit in the Interrupt Request Register (IRR[7:0]; addr 003–0B) is set to
report an interrupt event.
MIR[6]
—
SBIMODE[1]:
SBIMODE[0]:
MIR0:
MIR1:
MIR2:
MIR3:
MIR4:
MIR5:
MIR6:
MIR7:
6
6
MIR[5]
—
5
5
0 = no interrupt event in framer 0
1 = active interrupt event in framer 0
0 = no interrupt event in framer 1
1 = active interrupt event in framer 1
0 = no interrupt event in framer 2
1 = active interrupt event in framer 2
0 = no interrupt event in framer 3
1 = active interrupt event in framer 3
0 = no interrupt event in framer 4
1 = active interrupt event in framer 4
0 = no interrupt event in framer 5
1 = active interrupt event in framer 5
0 = no interrupt event in framer 6
1 = active interrupt event in framer 6
0 = no interrupt event in framer 7
1 = active interrupt event in framer 7
0 = Separate system bus interface mode for framer group 5
1 = Common, multiplexed system bus interface mode.
0 = Separate system bus interface mode for framer group 1
1 = Common, multiplexed system bus interface mode.
MIR[4]
—
4
4
Conexant
MIR[3]
MIR[3]
3
3
MIR[2]
MIR[2]
2
2
3.2 Global Control and Status Registers
MIR[1]
MIR[1]
1
1
3.0 Registers
–
–
8 (13
4 (9
MIR[0]
MIR[0]
0
0
–
12).
–
16).
3-9
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