cx28394 Conexant Systems, Inc., cx28394 Datasheet - Page 143

• Manufacturer Part Number: cx28394
• Description: Quad/x16/octal-t1/e1/j1 Framers
• Manufacturer: Conexant Systems, Inc.

CX28394/28395/28398
Quad/x16/Octal—T1/E1/J1 Framers
All events in ISR1 are from rising edge sources. Each event is latched active high and held until the processor
read clears ISR1. Each event triggers an interrupt if the corresponding IER1 bit is enabled [addr 012].
RBOP
RFULL2
RNEAR2
RMSG2
TDLERR2
TEMPTY2
TNEAR2
TMSG2
100054E
00A—Data Link 2 Interrupt Status (ISR1)
RBOP
7
BOP Codeword Received
in the RBOP register [addr 0A2].
Receive FIFO Full
write received data to a full FIFO causing the receive data link FIFO to overrun. In
unformatted modes (Pack6 and Pack8), RFULL is set when the receive FIFO is filled to the
MSG_FILL limit selected in register RDL2_FFC [addr 0B2].
Receive FIFO Near Full
selected in register RDL2_FFC [addr 0B2].
Message Received
available in the receiver FIFO.
Transmit FIFO Error
the FIFO without encountering an end of message [TDL2_EOM; addr 0B7]. The underrun
condition also forces transmission of an HDLC abort code.
Transmit FIFO Empty
write to a full FIFO. Overflow data is ignored by the transmit FIFO.
Transmit FIFO Near Empty
selected in register TDL2_FEC [addr 0B6].
Message Transmitted
is just beginning transmission.
RFULL2
6
RNEAR2
5
—
—
Set when a complete message or a partial message is received and
In HDLC modes, RFULL is set when the data link receiver attempts to
—
—
—
Set when the FIFO underruns as a result of the internal logic emptying
Set when a complete message has been transmitted and the closing flag
—
Set when the FIFO overflows as a result of the processor attempting to
—
Set when the receive FIFO fill level reaches the near full threshold
Set when a valid Bit Oriented Codeword is received and available
—
RMSG2
Set when the transmit FIFO level falls below the threshold
4
Conexant
TDLERR2
3
TEMPTY2
2
3.5 Interrupt Status Registers
TNEAR2
1
3.0 Registers
TMSG2
0
3-21