cx28394 Conexant Systems, Inc., cx28394 Datasheet - Page 49

• Manufacturer Part Number: cx28394
• Description: Quad/x16/octal-t1/e1/j1 Framers
• Manufacturer: Conexant Systems, Inc.

CX28394/28395/28398
Quad/x16/Octal—T1/E1/J1 Framers
Table 1-6. Hardware Signal Definitions (1 of 9)
100054E
RST*
SYSCKI
MCLK
SYNCMD
MOTO*
A[10:0]
A[11:0]
AD[7:0]
AS* (ALE)
CS1* , CS2*
Pin Label
Hardware Reset
System Clock
Processor Clock
Sync mode
Motorola Bus
Mode
Address Bus
Address Bus
Data Bus or
Address Data
Address Strobe
Chip Select
Signal Name
Device
Microprocessor Interface (MPU)
4, 5, 8
4, 5, 8
4, 5, 8
4, 5, 8
4, 5, 8
4, 5, 8
4, 5, 8
5, 8
4
5
(1)
Conexant
I/O
I/O
I
I
I
I
I
I
I
I
I
High-to-low-to-high cycle forces registers to their
power-up state and all PIO pins to the input state. RST*
is not mandatory since power-on reset circuit performs
an identical function. RST* must remain asserted for a
minimum of 2 processor clock cycles (MCLK or SYSCKI,
depending on SYNCMD selection).
Required 32.768 MHz clock for internal use. Supplied
from external source.
System applies MCLK in the range of 8–36 MHz for use
with synchronous MPU applications. MCLK is used
when SYNCMD = 1 and ignored when SYNCMD = 0.
Selects synchronous or asynchronous read/write timing
with respect to MCLK. Supports Intel- or Motorola-style
buses:
asynchronously controlled by CS* , DS*, and R/W*
signals.
CS* , DS*, and R/W* to determine valid read/write cycle
timing.
Selects Intel- or Motorola-style microprocessor
interface. DS*, R/W*, A[11:0], and AD[7:0] functions are
affected.
DS* is data strobe, and R/W* indicates read (high) or
write (low) data direction.
is ignored, A[11:8] is address, DS* is read strobe (RD* ),
and R/W* is write strobe (WR* ).
Address used to identify a register for subsequent
read/write data transfer cycle. In Motorola bus mode, all
eleven address bits (A[10:0]) are valid. In Intel bus
mode, only upper three bits (A[10:8]) are used.
Address used to identify a register for subsequent
read/write data transfer cycle. In Motorola bus mode, all
twelve address bits (A[11:0]) are valid. In Intel bus
mode, only upper four bits (A[11:8]) are used.
Multiplexed address/data (Intel) or data only(Motorola).
Refer to MOTO* signal definition.
For all processor bus modes, AS* falling edge
asynchronously latches address from A[11:0]
(Motorola) or A[11:8], AD[7:0] (Intel) to identify one
register for subsequent read/write data transfer cycle.
Active-low enables read/write decoder. Active high ends
current read or write cycle and places data bus output in
high impedance. CS1* is the chip select pin for framers
1 to 8, CS2* is the chip select for framers 9 to 16.
0 = Asynchronous Bus; read and write latches are
1 = Synchronous Bus; MCLK rising edge samples
0 = Motorola; AD[7:0] is data, A[11:0] is address,
1 = Intel; AD[7:0] is multiplexed address/data, A[7:0]
Definition
1.0 Product Description
1.2 Pin Assignments
1-31