cx28394 Conexant Systems, Inc., cx28394 Datasheet - Page 202

• Manufacturer Part Number: cx28394
• Description: Quad/x16/octal-t1/e1/j1 Framers
• Manufacturer: Conexant Systems, Inc.

3.0 Registers
3.15 Data Link Registers
RDL1[7:0]
RMSG1
RSTAT1
RMPTY1
RNEAR1
3-80
WORD1: Message Data
0A9—RDL #1 Status (RDL1_STAT)
RDL1[7]
—
7
7
Receive Message Data—Filled by the receiver data link, from LSB to MSB, with bits from the
selected channel. Processor reads 8-bit FIFO data during HDLC and Pack8 modes. During
Pack6 mode, only the six least significant bits RDL1[5:0] are filled.
In Progress Receive Message—Real time status of receive message sequencer is provided
mostly for processor polled applications. During HDLC modes, RMSG1 is high for the
interval between opening and closing FLAG characters to indicate the receiver is actively
filling FIFO locations (in which case RSTAT1 is also held high). RMSG1 is low while the
channel receives FLAG or Abort characters. During unformatted modes, RMSG1 is high
continuously.
Next FIFO Read Equals Message Status—For non-empty FIFO conditions (RMPTY1=0),
RSTAT1 indicates the next byte read from RDL1 returns WORD0 message status or WORD1
message data. Note that RSTAT1 equals zero if the FIFO is empty and there is no message in
progress. The processor polls RSTAT1 before reading RDL1 to determine how to interpret
RDL1 read byte value or the processor checks RSTAT1 in response to RMSG interrupt [ISR2;
addr 009].
Receive FIFO Empty—Indicates no data or status bytes are present in the receive data link
FIFO.
Receive FIFO Near Full—Indicates data link has filled receive FIFO to the near full threshold
level specified in FFC[5:0]. Upon reaching the near full level, the receiver updates the message
status byte [WORD0] placed on top of the FIFO and reports the current in progress message
with a Partial end of message status. The processor must read those filled FIFO locations to
clear RNEAR1 status indicator and to enable the next RNEAR interrupt.
RDL1[6]
—
0 = channel idle
1 = channel actively filling FIFO
0 = RDL1 byte equals Message Data (or empty FIFO, if RMTPY1=1)
1 = RDL1 byte equals Message Status (if RMPTY1=0)
0 = FIFO contains data or status as indicated by RSTAT1
1 = FIFO empty
0 = FIFO depth is below the near full level
1 = FIFO has been filled to the near full level
6
6
RDL1[5]
—
5
5
RDL1[4]
RMSG1
4
4
Conexant
RDL1[3]
RSTAT1
3
3
RMPTY1
RDL1[2]
2
2
Quad/x16/Octal—T1/E1/J1 Framers
CX28394/28395/28398
RDL1[1]
RNEAR1
1
1
RDL1[0]
RFULL1
100054E
0
0