cx28394 Conexant Systems, Inc., cx28394 Datasheet - Page 140

• Manufacturer Part Number: cx28394
• Description: Quad/x16/octal-t1/e1/j1 Framers
• Manufacturer: Conexant Systems, Inc.

3.0 Registers
3.5 Interrupt Status Registers
All events in ISR5 are from rising edge sources. Each event is latched active high and held according to the
LATCH_ERR bit [addr 046] and triggers an interrupt if the corresponding IER5 bit is enabled [addr 00E].
TSLIP
RSLIP
CERR
SERR
MERR
FERR
3-18
006—Error Interrupt Status (ISR5)
TSLIP
7
Transmit Slip Error—Two types of TSLIP buffer errors are reported: TFSLIP or TUSLIP.
Error type is reported separately in slip status [SSTAT; 0D9].
Receive Slip Error—Two types of RSLIP buffer errors are reported: RFSLIP or RUSLIP. Error
type is reported separately in slip status [SSTAT; 0D9].
CRC6/CRC4 Block Error—Applicable to ESF and MFAS modes only, read zero in other
modes. CERR indicates one or more bit errors found in received CRC-6 or CRC-4 checksum
block pattern.
CAS Pattern Error—Applicable only in E1 mode, read zero in T1 mode. SERR indicates one
or more bit errors in received TS16 Multiframe Alignment Signal (MAS).
MFAS Pattern Error—Applicable only in E1 mode (read zero in T1 mode)—Indicates one or
more bit errors in received MFAS alignment pattern.
Frame Error—Ft/Fs/T1DM/FPS/FAS Pattern Error—Indicates one or more Ft/Fs/FPS frame
bit errors or FAS pattern errors. Refer to
frame bits are monitored according to the selected receive framer mode.
RSLIP
0 = no error
1 = TSLIP error
0 = no error
1 = RSLIP error
0 = no error
1 = CRC error
0 = no error
1 = CAS error
0 = no error
1 = MFAS error
0 = no error
1 = frame error
6
—
5
—
4
Conexant
Tables A-1
CERR
3
through
SERR
2
Quad/x16/Octal—T1/E1/J1 Framers
A-6
for a description of which
CX28394/28395/28398
MERR
1
FERR
100054E
0