MC68HC908JG16FA MOTOROLA [Motorola, Inc], MC68HC908JG16FA Datasheet - Page 106
MC68HC908JG16FA
Manufacturer Part Number
MC68HC908JG16FA
Description
Microcontrollers
Manufacturer
MOTOROLA [Motorola, Inc]
Datasheet
1.MC68HC908JG16FA.pdf
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System Integration Module (SIM)
8.5.2 SIM Counter During Stop Mode Recovery
8.5.3 SIM Counter and Reset States
8.6 Exception Control
8.6.1 Interrupts
Technical Data
106
The SIM counter also is used for stop mode recovery. The STOP
instruction clears the SIM counter. After an interrupt, break, or reset, the
SIM senses the state of the short stop recovery bit, SSREC, in the
configuration register (CONFIG). If the SSREC bit is a logic 1, then the
stop recovery is reduced from the normal delay of 4096 OSCDCLK
cycles down to 2048 OSCDCLK cycles. This is ideal for applications
using canned oscillators that do not require long startup times from stop
mode. External crystal applications should use the full stop recovery
time, that is, with SSREC cleared in the configuration register (CONFIG).
External reset has no effect on the SIM counter. (See
for details.) The SIM counter is free-running after all reset states. (See
8.4.2 Active Resets from Internal Sources
internal reset recovery sequences.)
Normal, sequential program execution can be changed in three different
ways:
An interrupt temporarily changes the sequence of program execution to
respond to a particular event.
system interrupts.
•
•
•
Freescale Semiconductor, Inc.
For More Information On This Product,
Interrupts
– Maskable hardware CPU interrupts
– Non-maskable software interrupt instruction (SWI)
Reset
Break interrupts
System Integration Module (SIM)
Go to: www.freescale.com
Figure 8-8
flow charts the handling of
for counter control and
MC68HC908JG16
8.7.2 Stop Mode
MOTOROLA
—
Rev. 1.0
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