MC68HC908JG16FA MOTOROLA [Motorola, Inc], MC68HC908JG16FA Datasheet - Page 262
MC68HC908JG16FA
Manufacturer Part Number
MC68HC908JG16FA
Description
Microcontrollers
Manufacturer
MOTOROLA [Motorola, Inc]
Datasheet
1.MC68HC908JG16FA.pdf
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Input/Output (I/O) Ports
Technical Data
262
NOTE:
DDRB0 — Data Direction Register B Bit
Avoid glitches on PTB0 pin by writing to the port B data register before
changing data direction register B bit from 0 to 1.
Figure 14-7
When bit DDRB0 is a logic 1, reading address $0001 reads the PTB0
data latch. When bit DDRB0 is a logic 0, reading address $0001 reads
the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit.
the operation of the PTB0 pin.
Notes:
1. X = don’t care.
2. Hi-Z = high impedance.
3. Writing affects data register, but does not affect input.
DDRB0
This read/write bit control PTB0 data direction. Reset clears DDRB0,
configuring PTB0 pin as input.
Freescale Semiconductor, Inc.
Bit
0
1
For More Information On This Product,
1 = PTB0 pin configured as output
0 = PTB0 pin configured as input
READ DDRB ($0005)
WRITE DDRB ($0005)
WRITE PTB ($0001)
READ PTB ($0001)
PTB0 Bit
Go to: www.freescale.com
shows the port B I/O circuit logic.
Input/Output (I/O) Ports
X
X
(1)
Table 14-3. Port B Pin Functions
Figure 14-7. Port B I/O Circuit
RESET
I/O Pin Mode
Input, Hi-Z
Output
(2)
DDRB0
PTB0
Read/Write
Accesses
to DDRB
DDRB0
DDRB0
Table 14-3
MC68HC908JG16
Read
PTB0
Accesses to PTB
Pin
summarizes
MOTOROLA
PTB0
—
Write
PTB0
Rev. 1.0
(3)
PTB0
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