MC68HC908JG16FA MOTOROLA [Motorola, Inc], MC68HC908JG16FA Datasheet - Page 293

• Manufacturer Part Number: MC68HC908JG16FA
• Description: Microcontrollers
• Manufacturer: MOTOROLA [Motorola, Inc]

17.4 I/O Signals
17.4.1 OSCDCLK
17.4.2 STOP Instruction
17.4.3 COPCTL Write
17.4.4 Power-On Reset
MC68HC908JG16
MOTOROLA
NOTE:
—
Rev. 1.0
A COP reset pulls the RST pin low for 32 OSCDCLK cycles and sets the
COP bit in the SIM reset status register (SRSR).
In monitor mode, the COP is disabled if the RST pin or the IRQ is held
at V
Place COP clearing instructions in the main program and not in an
interrupt subroutine. Such an interrupt subroutine could keep the COP
from generating a reset even while the main program is not working
properly.
The following paragraphs describe the signals shown in
OSCDCLK is the crystal oscillator clock doubler output signal. Its
frequency is two times the crystal frequency.
The STOP instruction clears the COP prescaler.
Writing any value to the COP control register (COPCTL) (see
Control
of the prescaler. Reading the COP control register returns the low byte
of the reset vector.
The power-on reset (POR) circuit clears the COP prescaler 4096
OSCDCLK cycles after power-up.
Freescale Semiconductor, Inc.
TST
For More Information On This Product,
. During the break state, V
Computer Operating Properly (COP)
Register) clears the COP counter and clears bits 12 through 5
Go to: www.freescale.com
TST
on the RST pin disables the COP.
Computer Operating Properly (COP)
Figure
Technical Data
17.5 COP
I/O Signals
17-1.
293