MC68HC908JG16FA MOTOROLA [Motorola, Inc], MC68HC908JG16FA Datasheet - Page 97

• Manufacturer Part Number: MC68HC908JG16FA
• Description: Microcontrollers
• Manufacturer: MOTOROLA [Motorola, Inc]

MC68HC908JG16
MOTOROLA
Signal Name
OSCDCLK
OSCOUT
PORRST
PIN LOGIC
IRST
RESET
R/W
IDB
IAB
INTERNAL
PULL-UP
—
Rev. 1.0
VDD
Table 8-1. SIM Module Signal Name Conventions
Clock doubler output which has twice the frequency of OSC1 from the oscillator
The OSCDCLK frequency divided by two. This signal is again divided by two in the
SIM to generate the internal bus clocks.
(Bus clock = OSCDCLK ÷ 4 = OSCXCLK ÷ 2)
Internal address bus
Internal data bus
Signal from the power-on reset module to the SIM
Internal reset signal
Read/write signal
SIM RESET STATUS REGISTER
Freescale Semiconductor, Inc.
RESET PIN CONTROL
For More Information On This Product,
POR CONTROL
STOP/WAIT
CONTROL
CONTROL
AND PRIORITY DECODE
Figure 8-1. SIM Block Diagram
INTERRUPT CONTROL
CLOCK
System Integration Module (SIM)
Go to: www.freescale.com
CLOCK GENERATORS
RESET
COUNTER
SIM
÷ 2
Description
CONTROL
MASTER
RESET
LVI RESET (FROM LVI MODULE)
USB RESET (FROM USB MODULE)
MODULE STOP
MODULE WAIT
CPU STOP (FROM CPU)
CPU WAIT (FROM CPU)
SIMOSCEN (TO OSCILLATOR)
COP CLOCK
OSCDCLK (FROM OSC)
OSCOUT (FROM OSC)
INTERNAL CLOCKS
ILLEGAL OPCODE (FROM CPU)
ILLEGAL ADDRESS (FROM ADDRESS
MAP DECODERS)
COP TIMEOUT (FROM COP MODULE)
CPU INTERFACE
INTERRUPT SOURCES
System Integration Module (SIM)
Technical Data
Introduction
97