MC68HC908JG16FA MOTOROLA [Motorola, Inc], MC68HC908JG16FA Datasheet - Page 292

• Manufacturer Part Number: MC68HC908JG16FA
• Description: Microcontrollers
• Manufacturer: MOTOROLA [Motorola, Inc]

Computer Operating Properly (COP)
17.3 Functional Description
Technical Data
292
INTERNAL RESET SOURCES
(COPRS FROM CONFIG)
RESET VECTOR FETCH
(COPD FROM CONFIG)
STOP INSTRUCTION
COPEN (FROM SIM)
NOTE:
COPCTL WRITE
COPCTL WRITE
COP RATE SEL
COP DISABLE
OSCDCLK
RESET
Figure 17-1
The COP counter is a free-running 6-bit counter preceded by a 12-bit
prescaler counter. If not cleared by software, the COP counter overflows
and generates an asynchronous reset after 2
OSCDCLK cycles, depending on the state of the COP rate select bit,
COPRS, in configuration register 1. With a 2
overflow option, a 24MHz OSCDCLK (12MHz crystal) gives a COP
timeout period of 10.92ms. Writing any value to location $FFFF before
an overflow occurs prevents a COP reset by clearing the COP counter
and stages 12 through 5 of the prescaler.
Service the COP immediately after reset and before entering or after
exiting stop mode to guarantee the maximum time before the first COP
counter overflow.
Freescale Semiconductor, Inc.
For More Information On This Product,
Figure 17-1. COP Block Diagram
Computer Operating Properly (COP)
12-BIT COP PRESCALER
Go to: www.freescale.com
shows the structure of the COP module.
COP CLOCK
COP COUNTER
6-BIT COP COUNTER
CLEAR
18
RESET STATUS REGISTER
18
MC68HC908JG16
– 2
– 2
RESET CIRCUIT
4
4
OSCDCLK cycle
or 2
13
– 2
MOTOROLA
4
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Rev. 1.0